公开(公告)号：US07485917B2

公开(公告)日：2009-02-03

申请号：US11390144

申请日：2006-03-28

Applicant: Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

Inventor： Ching-Hung Fu ,  Hung-Kwei Liao ,  Chien-Chung Lu

IPC: H01L29/788

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/42328

Abstract: A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.

Abstract translation: 公开了一种分离栅闪存单元，其包括其上具有第一绝缘层的半导体衬底和具有第一宽度的浮动栅极。 电池还依次包括浮置栅极上的第二绝缘层，控制栅极和盖子。 盖层，控制栅极和第二绝缘层具有小于第一宽度的相同的第二宽度。 电池还包括半导体衬底上的第三绝缘层，控制栅极的侧壁，第二绝缘层，浮置栅极和第一绝缘层。 此外，设置形成在第三绝缘层上的擦除栅极。

公开(公告)号：US20090014787A1

公开(公告)日：2009-01-15

申请号：US11969702

申请日：2008-01-04

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

Abstract translation: 功率MOSFET结构包括在单元区域中的至少一个第一栅极和位于半导体衬底中的至少一个外围的第二栅极。 第一和第二栅极电连接，并且第二栅极连接到触点，以便电连接到用于传输栅极控制信号的接合焊盘。 半导体衬底包括第一半导体层，第二半导体层和第三半导体层。 第一和第三半导体层是第一导电类型，例如n型，并且第二半导体层是第二导电类型，例如p型。 第一和第三半导体层分别用作源极和漏极。

公开(公告)号：US20090014705A1

公开(公告)日：2009-01-15

申请号：US12127712

申请日：2008-05-27

Applicant: Hong-Hui Hsu ,  Frederick T. Chen ,  Ming-Jer Kao

Inventor： Hong-Hui Hsu ,  Frederick T. Chen ,  Ming-Jer Kao

IPC: H01L29/04 ,  H01L21/77

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer.

Abstract translation: 提供了相变存储器件。 相变存储器件包括衬底。 在基板上形成第一导电层。 在第一导电层上形成加热电极，与第一导电层电连接，其中加热电极包括碳纳米管（CNT）。 相变材料层覆盖加热电极。 第二导电层形成在相变材料层上，并且电连接到相变材料层。

公开(公告)号：US20090008781A1

公开(公告)日：2009-01-08

申请号：US12211068

申请日：2008-09-15

Applicant: Bai-rou Ni ,  Fang-Yu Yeh ,  Yueh-Chuan Lee

Inventor： Bai-rou Ni ,  Fang-Yu Yeh ,  Yueh-Chuan Lee

IPC: H01L29/51

CPC classification number: H01L21/28061 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/51 ,  H01L29/66583

Abstract: A semiconductor device structure includes a substrate, a first conductive layer over the substrate, a second conductive layer between the first conductive layer and the substrate and extending over the sidewalls of the first conductive layer, a dielectric layer between the second conductive layer and the substrate, a cap layer over the first conductive layer and the second conductive layer, and a liner layer on the sidewalls of the second conductive layer.

Abstract translation: 半导体器件结构包括衬底，在衬底上的第一导电层，在第一导电层和衬底之间并在第一导电层的侧壁上延伸的第二导电层，在第二导电层和衬底之间的介电层 ，在第一导电层和第二导电层之上的覆盖层，以及在第二导电层的侧壁上的衬层。

公开(公告)号：US20090008621A1

公开(公告)日：2009-01-08

申请号：US11966584

申请日：2007-12-28

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å.

Abstract translation: 提供了相变存储元件。 本发明的实施例的相变存储元件包括具有凹部的相变材料层和具有延伸部分的加热器，其中加热器的延伸部分楔入相变材料层的凹部 。 具体来说，加热器的延伸部分的长度为10〜5000。

公开(公告)号：US20080318392A1

公开(公告)日：2008-12-25

申请号：US11864037

申请日：2007-09-28

Applicant: Kuo-Hsiang Hung ,  Chuan-Chi Chen

Inventor： Kuo-Hsiang Hung ,  Chuan-Chi Chen

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the uncovered inner wall of the trench; removing the first dielectric layer; and forming a second dielectric layer to cover the trench and form a void inside the trench.

Abstract translation: 提供了形成浅沟槽隔离结构的方法。 该方法包括以下步骤：为基底提供“v”形沟槽，形成第一介电层以覆盖沟槽内壁的上部; 进行第一蚀刻工艺以拉回沟槽的未覆盖的内壁; 去除第一电介质层; 以及形成第二电介质层以覆盖沟槽并在沟槽内形成空隙。

公开(公告)号：US20080316803A1

公开(公告)日：2008-12-25

申请号：US11968041

申请日：2007-12-31

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

IPC: G11C7/12

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.

Abstract translation: 相变存储器的感测电路。 感测电路包括数据电流源和参考电流源，存储存储器件和参考存储器件，存储开关和参考开关，辅助电流源和比较器。 存储存储器件和参考存储器件的第一端子分别耦合到数据电流源和参考电流源。 存储开关和参考开关分别耦合到存储存储器件和参考存储器件的第二端子。 辅助电流源动态地耦合到存储存储器件和参考存储器件的第一端子。 比较器耦合到存储存储器件和参考存储器件的第一端子。

公开(公告)号：US20080272358A1

公开(公告)日：2008-11-06

申请号：US11836093

申请日：2007-08-08

Applicant: Yung-Fa Lin ,  Te-Chun Wang

Inventor： Yung-Fa Lin ,  Te-Chun Wang

IPC: H01L47/00

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括形成在衬底上的底部电极。 在底部电极上方形成第一电介质层。 加热电极形成在第一电介质层中并且部分地突出在第一电介质层上，其中加热电极包括嵌入在第一电介质层内的本征部分，堆叠在本征部分上的还原部分和围绕侧壁的氧化物间隔物 的减少部分。 在第一电介质层上形成相变材料层并覆盖加热电极，相变材料层接触加热电极的减少部分的顶表面。 顶部电极形成在相变材料层上并与相变材料层接触。

公开(公告)号：US20080265311A1

公开(公告)日：2008-10-30

申请号：US11756529

申请日：2007-05-31

Applicant: Ming Tang ,  Frank Chen

Inventor： Ming Tang ,  Frank Chen

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0657 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/78

Abstract: A vertical transistor comprises a substrate having a step structure, two doped regions positioned in the substrate at the two sides of the step structure, and a carrier channel positioned in the substrate between the two doped regions, wherein the step structure includes an inclined edge and the width of the carrier channel at the inclined edge is larger than the width of the doped regions. The step structure comprises two non-rectangular surfaces, such as the trapezoid or triangular surfaces, and a rectangular surface. The non-rectangular surfaces connect to the doped regions, and the rectangular surface is perpendicular to the non-rectangular surface.

Abstract translation: 垂直晶体管包括具有阶梯结构的衬底，位于阶梯结构两侧的衬底中的两个掺杂区域和位于两个掺杂区域之间的衬底中的载流子通道，其中阶梯结构包括倾斜边缘和 倾斜边缘处的载流子通道的宽度大于掺杂区域的宽度。 台阶结构包括两个非矩形表面，例如梯形或三角形表面，以及矩形表面。 非矩形表面连接到掺杂区域，矩形表面垂直于非矩形表面。

公开(公告)号：US07436526B2

公开(公告)日：2008-10-14

申请号：US11669165

申请日：2007-01-31

Applicant: Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

Inventor： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC: B29C65/00 ,  B29C65/02 ,  B32B37/00 ,  B32B38/00 ,  C23C16/52 ,  C23C14/54 ,  G01B11/14 ,  G01B11/28

CPC classification number: C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

Abstract: A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

Abstract translation: 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。