公开(公告)号：US09197197B2

公开(公告)日：2015-11-24

申请号：US14050203

申请日：2013-10-09

Applicant: STMicroelectronics S.A. ,  Mentor Graphics Corporation

Inventor： Anna Asquini ,  Vincent Vallet

IPC: H03L7/00 ,  H03K3/017 ,  H03K5/1252 ,  G06F1/10 ,  G06F1/12

CPC classification number: H03K3/017 ,  G06F1/10 ,  G06F1/12 ,  H03K5/1252

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract translation: 一种占空比保护电路，包括适于在输入线路上接收第一时钟信号的第一同步装置，并且响应于第一时钟信号的第一时钟转换而产生第二时钟信号的第一时钟转变; 以及复位电路，其耦合到所述输入线并且适于通过在所述第一时钟信号的所述第一时钟转换之后复位所述第一同步器件时间延迟来产生所述第二时钟信号的第二时钟转变。

公开(公告)号：US09165861B2

公开(公告)日：2015-10-20

申请号：US14287343

申请日：2014-05-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Simon Gousseau ,  Yann Beilliard

IPC: H01L23/427 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.

Abstract translation: 用于在衬底内部生产至少一个穿硅的方法可包括在衬底的第一侧从衬底的第一侧形成空腔，直到导电部分出现。 该方法还可以包括在空腔的底部和壁上形成导电层，并且至少部分地在空腔外部的第一侧上形成导电层。 该方法还可以包括用至少一种相变材料至少部分地填充空腔。 另一方面涉及三维综合结构。

公开(公告)号：US09159402B2

公开(公告)日：2015-10-13

申请号：US13539577

申请日：2012-07-02

Applicant: Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

Inventor： Vivek Asthana ,  Malathi Kar ,  Philippe Galy ,  Jean Jimenez

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/4125 ,  G11C11/419

Abstract: An SRAM bitcell includes first and second CMOS inverters connected as a latch defining a true node and a complement node. The bitcell further includes true and complement bitline nodes. A first direct connection is provided between the true bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the second CMOS inverter. A second direct connection is provided between the complement bitline node and a back gate of at least a p-channel transistor, and perhaps also an n-channel transistor, in the first CMOS inverter. A first pass transistor is coupled between the true bitline node and the true node, and a second pass transistor is coupled between the complement bitline node and the complement node. Direct connections are also provided between a wordline and the back gates of each of the first and second pass transistors.

Abstract translation: SRAM位单元包括作为锁存器连接的第一和第二CMOS反相器，其定义真实节点和补码节点。 位单元还包括真和补码位线节点。 在第二CMOS反相器中，在真位线节点和至少p沟道晶体管的背栅极之间提供第一直接连接，以及可能还提供n沟道晶体管。 在第一CMOS反相器中的补码位线节点和至少p沟道晶体管的背栅极之间提供第二直接连接，以及可能还提供n沟道晶体管。 第一传输晶体管耦合在真位元节点和真节点之间，第二传输晶体管耦合在补码位线节点和补码节点之间。 在字线和第一和第二传输晶体管的每个的后栅极之间也提供直接连接。

公开(公告)号：US20150249179A1

公开(公告)日：2015-09-03

申请号：US14627038

申请日：2015-02-20

Applicant: STMicroelectronics SA

Inventor： Bruno Rauber

IPC: H01L31/112 ,  H01L31/02 ,  H01L31/028

CPC classification number: H01L27/1446 ,  H01L31/101 ,  H01L31/11

Abstract: A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region.

Abstract translation: 在绝缘体上硅（SOI）型半导体层中形成光检测器。 光电检测器包括第一导电类型的第一区域和第二区域，第二区域通过第二导电类型的中心区域彼此分开，以便限定光电晶体管。 半导体层的横向表面被配置为接收照明。 横向表面垂直于中心区域的上表面延伸。

公开(公告)号：US09092590B2

公开(公告)日：2015-07-28

申请号：US14105382

申请日：2013-12-13

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Matthieu Le Boulaire ,  Jean-Philippe Noel

IPC: G06F17/50 ,  H01L21/84

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/84

Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Abstract translation: 包括排列成一排的第一和第二FDSOI UTBOX单元的IC，其中第一和第二FDSOI UTBOX单元排列成一行，其中第一和第二FOSOI UTBOX单元布置成具有和接地平面以上的nMOS晶体管和N型阱，以及配置有接地平面以上的铅垂和P 型井，N型阱和P型阱布置在行轴的任一侧，其中第二个包括防止天线效应的二极管或阱分接电池，第二电池包括P型阱 被布置成pMOS晶体管的P型阱的对准并且包括以nMOS晶体管的N型阱的排列方式布置的N型阱，第二单元包括耦合到其P型阱的金属连接 并且连接到具有N型井的高级金属连接元件排列的铅垂，金属连接在轴的任一侧延伸。

公开(公告)号：US09083324B2

公开(公告)日：2015-07-14

申请号：US14024508

申请日：2013-09-11

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Andreia Cathelin ,  Janusz Grzyb ,  Yan Zhao

IPC: H03K3/03 ,  H03L7/099 ,  H03B27/00 ,  H03L7/23

CPC classification number: H03K3/0315 ,  H03B27/00 ,  H03L7/099 ,  H03L7/23

Abstract: A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator.

Abstract translation: 频率振荡器包括具有串联耦合的N个反相器的环形振荡器，其中N是等于3或更大的奇整数。 第一滤波器耦合在第一反相器的输出节点和频率振荡器的输出线之间。 第二滤波器耦合在第二反相器的输出节点和频率振荡器的输出线之间。

公开(公告)号：US09029955B2

公开(公告)日：2015-05-12

申请号：US13933396

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/732 ,  H01L29/06

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20150116029A1

公开(公告)日：2015-04-30

申请号：US14523996

申请日：2014-10-27

Applicant: STMicroelectronics SA

Inventor： Antoine Litty ,  Sylvie Ortolland

IPC: H01L29/78 ,  H03K17/687 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/78624 ,  H01L29/78648 ,  H03K17/687

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract translation: 延伸漏极晶体管形成在绝缘层的一侧上的半导体层中，半导体区域布置在绝缘层的另一侧上。 半导体区域包括布置在源极的前面的第一导电类型的第一部分和栅极的至少一个较大部分和布置在延伸漏极区域的至少较大部分的前面的第二导电类型的第二部分 所述第一和第二部分中的每一个耦合到连接垫。

公开(公告)号：US09018729B2

公开(公告)日：2015-04-28

申请号：US13895715

申请日：2013-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raul Andres Bianchi ,  Pascal Fonteneau

IPC: H01L23/58 ,  H01L31/0256 ,  H01L27/144 ,  H01L31/18 ,  H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L31/0256 ,  H01L27/144 ,  H01L29/0684 ,  H01L29/66113 ,  H01L29/866 ,  H01L31/1892

Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.

Abstract translation: 一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

公开(公告)号：US09018078B2

公开(公告)日：2015-04-28

申请号：US13751489

申请日：2013-01-28

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Benoit Sklenard ,  Perrine Batude

IPC: H01L21/46 ,  H01L23/58 ,  H01L21/02 ,  H01L27/06 ,  H01L27/12 ,  H01L21/822

CPC classification number: H01L23/585 ,  H01L21/02038 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract translation: 一种用于制造集成电路的方法，包括以下步骤：在第一半导体层上形成第一晶体管; 在所述第一半导体层和所述第一晶体管之上沉积第一绝缘层，以及对所述第一绝缘层进行调平; 在第一绝缘层上方沉积导电层，并用第二绝缘层覆盖导电层; 将半导体晶片接合到所述第二绝缘层; 使半导体晶片变薄以获得第二半导体层; 以及在所述第二半导体层上形成第二晶体管。