公开(公告)号：US20240355751A1

公开(公告)日：2024-10-24

申请号：US18136722

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Sanjay THARMARAJAH ,  Hiroki TANAKA ,  Clayton BRENNER

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L21/4846

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a substrate and a pad on the substrate. In an embodiment, a layer is over the pad and the substrate, and an opening through the layer is above the pad. In an embodiment, sidewalls of the layer define the opening. In an embodiment, an undercut at an end of the opening adjacent to the pad is provided, where the undercut is positioned between the pad and the layer. In an embodiment, a bump is in the opening, where the bump at least partially fills the undercut

公开(公告)号：US20240355682A1

公开(公告)日：2024-10-24

申请号：US18761493

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US20240355111A1

公开(公告)日：2024-10-24

申请号：US18758110

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Alexey M. Supikov ,  Ronald Tadao Azuma

IPC: G06V10/82 ,  G06T7/20 ,  G06T7/90

CPC classification number: G06V10/82 ,  G06T7/20 ,  G06T7/90 ,  G06T2207/10024

Abstract: Example apparatus disclosed herein are to train a neural network based on initial video frames of an input video to generate neural representations of the initial video frames, the neural network having a first group of layers and a second group of layers, the first group of layers to be retrained for subsequent video frames after the initial video frames, the second group of layers to be selectively frozen for the subsequent video frames. Disclosed example apparatus are also to select a layer of the second group of layers to be unfrozen for a first video frame subsequent to the initial video frames, and retrain the first group of layers and the selected layer of the second group of layers to generate a neural representation of the first video frame, unselected ones of the second group of layers to remain frozen in the neural representation of the first video frame.

公开(公告)号：US20240355032A1

公开(公告)日：2024-10-24

申请号：US18436688

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Prasoonkumar Surti ,  Murali Ramadoss

IPC: G06T15/00 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

CPC classification number: G06T15/005 ,  G06F9/5027 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T2215/16

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

公开(公告)号：US20240354190A1

公开(公告)日：2024-10-24

申请号：US18759122

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Junjing SHI ,  Wei YANG ,  Amir Ali RADJAI ,  Hongjiu LU

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1004

Abstract: Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.

公开(公告)号：US20240354107A1

公开(公告)日：2024-10-24

申请号：US18754447

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Frank Hady ,  Christopher J. Hughes ,  Scott Peterson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30047 ,  G06F9/321 ,  G06F9/3836

Abstract: In one example, a processor includes: at least one core to execute instructions; and at least one cache memory coupled to the at least one core, the at least one cache memory to store data, at least some of the data a copy of data stored in a memory. The at least one core is to determine whether to conditionally offload a sequence of instructions for execution on a compute circuit associated with the memory, based at least in part on whether one or more first data is present in the at least one cache memory, the one or more first data for use during execution of the sequence of instructions. Other embodiments are described and claimed.

公开(公告)号：US20240351892A1

公开(公告)日：2024-10-24

申请号：US18759055

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Krishnendu Saha ,  Chethan Holla ,  Hari Shanker Thakur

IPC: C01B33/158 ,  C01B33/159 ,  C09D183/04 ,  G06F1/20 ,  H05K5/02

CPC classification number: C01B33/1585 ,  C01B33/159 ,  C09D183/04 ,  G06F1/206 ,  H05K5/02 ,  C01P2006/32

Abstract: Aerogel including low thermal conductivity gases and related apparatus and methods are disclosed. An example aerogel disclosed herein includes a framework including a plurality of pores and a gas in at least one of the plurality of pores, the gas having a lower thermal conductivity than air.

公开(公告)号：US20240351200A1

公开(公告)日：2024-10-24

申请号：US18759669

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Edgar Macias Garcia ,  Leobardo Campos Macias ,  Hector Cordourier Maruri ,  Rafael De La Guardia Gonzalez ,  David Gonzalez Aguirre ,  Alejandro Ibarra Von Borstel ,  Paulo Lopez Meyer ,  Javier Turek ,  Julio Zamora Esquivel

IPC: B25J9/16

CPC classification number: B25J9/163 ,  B25J9/161 ,  B25J9/1664 ,  B25J9/1682

Abstract: An apparatus, including: an interface configured to receive a target end-effector pose of a cobot; processing circuitry configured to: generate in a generic robot model a joint trajectory based on the target end-effector pose; employ a trained neural network model to map the joint trajectory generated in the generic robot model into a cobot model; and generate a movement instruction to control a movement of the cobot based on the joint trajectory mapped to the cobot model, wherein the generic robot model has a number of degrees of freedom that is equal to or greater than that of the cobot model.

公开(公告)号：USD1047998S1

公开(公告)日：2024-10-22

申请号：US29845962

申请日：2022-07-12

Applicant: Intel Corporation

Designer： Mikko Makinen ,  Gustavo Fricke

Abstract: FIG. 1 is a front, right perspective view of a laptop.
FIG. 2 is a front view of the laptop of FIG. 1.
FIG. 3 is a rear view of the laptop of FIG. 1.
FIG. 4 is a right side view of the laptop of FIG. 1.
FIG. 5 is a left side view of the laptop of FIG. 1.
FIG. 6 is a top view of the laptop pf FIG. 1; and,
FIG. 7 is a bottom view of the laptop of FIG. 1.

公开(公告)号：US12126706B2

公开(公告)日：2024-10-22

申请号：US17134351

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  John Sell

IPC: G06F21/78 ,  G06F21/60 ,  H04L9/00 ,  H04L9/06 ,  H04L9/32

CPC classification number: H04L9/002 ,  G06F21/602 ,  H04L9/0643 ,  H04L9/3242

Abstract: Detailed herein are embodiments which allow for integrity protected access control to provide defense against deterministic software attacks. Software attacks such as rowhammer attacks which target the TD bit itself are defended against using cryptographic integrity which the data itself is protected by the TD-bit alone. As such, software is reduced to performing only non-deterministic attacks (e.g., random corruption), but all the deterministic attacks are defended against. Additionally, integrity-protected access control bits are protected against simple hardware attacks where the adversary with physical access to the machine can flip TD bits to get ciphertext access in software which can break confidentiality.