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    Strategic memory cell reliability management
    441.
    发明授权
    Strategic memory cell reliability management 有权

    公开(公告)号：US12112057B2

    公开(公告)日：2024-10-08

    申请号：US17861233

    申请日：2022-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Daniele Balluchi

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

    Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

    Data burst suspend mode using multi-level signaling
    442.
    发明授权
    Data burst suspend mode using multi-level signaling 有权

    公开(公告)号：US12111781B2

    公开(公告)日：2024-10-08

    申请号：US18119576

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

    Memory cache management based on storage capacity for parallel independent threads
    443.
    发明授权
    Memory cache management based on storage capacity for parallel independent threads 有权

    公开(公告)号：US12111761B2

    公开(公告)日：2024-10-08

    申请号：US17688506

    申请日：2022-03-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca Bert

    IPC: G06F12/0808 ,  G06F12/0871

    CPC classification number: G06F12/0808 ,  G06F12/0871 ,  G06F2212/50

    Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.

    Redundant array management techniques
    444.
    发明授权
    Redundant array management techniques 有权

    公开(公告)号：US12111724B2

    公开(公告)日：2024-10-08

    申请号：US17648395

    申请日：2022-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1076

    Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

    EDGE INTERFACE PLACEMENTS TO ENABLE CHIPLET ROTATION INTO MULTI-CHIPLET CLUSTER
    445.
    发明公开
    EDGE INTERFACE PLACEMENTS TO ENABLE CHIPLET ROTATION INTO MULTI-CHIPLET CLUSTER 审中-公开

    公开(公告)号：US20240332257A1

    公开(公告)日：2024-10-03

    申请号：US18734765

    申请日：2024-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Michael G. Placke ,  Tony Brewer

    IPC: H01L25/065 ,  H01L23/00

    CPC classification number: H01L25/0655 ,  H01L24/16

    Abstract: A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.

    APPARATUSES AND METHODS FOR REDUCING STANDBY CURRENT IN MEMORY ARRAY ACCESS CIRCUITS
    450.
    发明公开
    APPARATUSES AND METHODS FOR REDUCING STANDBY CURRENT IN MEMORY ARRAY ACCESS CIRCUITS 审中-公开

    公开(公告)号：US20240331763A1

    公开(公告)日：2024-10-03

    申请号：US18591798

    申请日：2024-02-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： TAKAMASA SUZUKI ,  NOBUO YAMAMOTO ,  IZUMI NAKAI

    IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

    CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

    Abstract: Apparatuses and methods for reducing standby current in memory array access circuits are disclosed. An example apparatus includes a activation voltage supply line and a sense amplifier coupled to the activation voltage supply line. The sense amplifier is configured to be activated by an activation voltage provided on the activation voltage supply line. A read-write circuit is coupled to a pair of local input/output lines and a pair of global input/output lines, and further coupled to the activation voltage supply line. The read-write circuit is configured to drive the pair global input/output lines based on voltages of the pair of local input/output lines when activated for a read operation and further configured to drive the pair of local input/output lines based on voltages of the pair of global input/output lines when activated for a write operation.

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