公开(公告)号：US20050098899A1

公开(公告)日：2005-05-12

申请号：US10897222

申请日：2004-07-22

Applicant: Gregory Smith

Inventor： Gregory Smith

IPC: C23F1/02 ,  C23F4/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/97 ,  H01L2924/00

Abstract: The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

Abstract translation: 通过绝缘层的接触开口形成为具有直的侧壁部分和碗形的侧壁部分。 碗状侧壁部分靠近绝缘层的顶部，以在顶部相对于底部提供接触开口的扩大直径。 然后在接触开口中形成与下导电层电接触的导电材料。 导电材料形成具有扩大的头部的塞子，例如钉头或平的热螺丝形状。 扩大的头部保护硅和阻挡层（如果存在）在接触件内被任何随后的各向异性蚀刻腐蚀。 因此，当诸如铝的电互连层形成在接触插塞上方时，插塞充当蚀刻停止件，以防止在接触开口内蚀刻阻挡层的阻挡层。

公开(公告)号：US20050088872A1

公开(公告)日：2005-04-28

申请号：US10695238

申请日：2003-10-27

Applicant: Herman Ma

Inventor： Herman Ma

IPC: G11C13/00 ,  G11C16/02 ,  G11C16/26 ,  H01L27/105 ,  G11C5/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A circuit and method are disclosed for a memory device, such as a phase change memory. Specifically, there is disclosed a memory having a plurality of columns of memory cells, with each column of memory cells being coupled to a bit or data line. Each memory cell includes a programmable resistive element coupled in series with a select transistor. Each bit line is coupled to a distinct reference cell and a distinct transistor. The transistor is coupled between the corresponding bit line and a reference voltage, such as ground. During a memory read operation, the transistor, reference cell and addressed memory cell form a differential amplifier circuit. The output of the differential amplifier circuit is coupled to the data output terminals of the phase change memory.

Abstract translation: 公开了一种用于诸如相变存储器之类的存储器件的电路和方法。 具体地，公开了具有多列存储器单元的存储器，每列存储器单元耦合到位或数据线。 每个存储单元包括与选择晶体管串联耦合的可编程电阻元件。 每个位线耦合到不同的参考单元和不同的晶体管。 晶体管耦合在对应的位线和参考电压之间，例如接地。 在存储器读取操作期间，晶体管，参考单元和寻址的存储单元形成差分放大器电路。 差分放大器电路的输出耦合到相变存储器的数据输出端子。

公开(公告)号：US20050088222A1

公开(公告)日：2005-04-28

申请号：US10695293

申请日：2003-10-27

Applicant: David McClure

Inventor： David McClure

IPC: G05F1/10 ,  G05F3/24

CPC classification number: G05F3/247

Abstract: A voltage regulator having a plurality of current sources and adapted to make available current to a circuit, such as a memory device. One or more of the plurality of current sources is selectively enabled/disabled to provide either of two non-zero, distinct current levels to the circuit depending on a logic value of the chip enable signal. The chip enable signal is input to the circuit to enable/disable the circuit to perform various operations.

Abstract translation: 一种电压调节器，具有多个电流源并且适于向电路（例如存储器件）提供可用电流。 多个电流源中的一个或多个被选择性地使能/禁止，以根据芯片使能信号的逻辑值向电路提供两个非零的不同电流电平。 芯片使能信号被输入到电路以使能/禁止电路执行各种操作。

公开(公告)号：US06865665B2

公开(公告)日：2005-03-08

申请号：US09751331

申请日：2000-12-29

Applicant: Anthony X. Jarvis

Inventor： Anthony X. Jarvis

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/34

CPC classification number: G06F12/0888 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3861 ,  G06F12/0859

Abstract: There is disclosed a data processor for stalling the instruction execution pipeline after a cache miss and re-loading the correct cache data into any bypass devices before restarting the pipeline. The data processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of architectural registers for receiving the data values from the data cache; 4) bypass circuitry for transferring a first data value from the data cache directly to a functional unit in one of the N processing stages without first storing the first data value in a destination one of the plurality of architectural registers; and 5) a cache refill controller for detecting that a cache miss has occurred at a first address associated with the first data value, receiving a missed cache line from a main memory coupled to the data processor, and causing the first data value to be transferred from the missed cache line to the functional unit.

Abstract translation: 公开了一种数据处理器，用于在高速缓存未命中之后停止指令执行流水线，并在重新启动流水线之前将正确的高速缓存数据重新加载到任何旁路设备中。 数据处理器包括：1）包括N个处理级的指令执行流水线，N个处理级中的每一个执行与由指令执行管线执行的待处理指令相关联的多个执行步骤之一; 2）用于存储待决指令使用的数据值的数据高速缓存; 3）多个架构寄存器，用于从数据高速缓存接收数据值; 4）旁路电路，用于将第一数据值从数据高速缓存直接传送到N个处理阶段之一中的功能单元，而不首先将第一数据值存储在多个架构寄存器的目的地中; 以及5）高速缓存补充控制器，用于检测在与所述第一数据值相关联的第一地址处发生了高速缓存未命中，从耦合到所述数据处理器的主存储器接收错过的高速缓存行，并且使所述第一数据值被传送 从错过的高速缓存行到功能单元。

公开(公告)号：US06861860B2

公开(公告)日：2005-03-01

申请号：US10150225

申请日：2002-05-17

Applicant: Riccardo Maggi ,  Massimo Scipioni

Inventor： Riccardo Maggi ,  Massimo Scipioni

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2856 ,  G01R31/2877

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

公开(公告)号：US06856542B2

公开(公告)日：2005-02-15

申请号：US10164245

申请日：2002-06-04

Applicant: Anirban Roy ,  Luca Giovanni Fasoli

Inventor： Anirban Roy ,  Luca Giovanni Fasoli

IPC: H01L21/82 ,  G11C14/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1736 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11803

Abstract: A programmable logic device (PLD) and method for fabricating the PLD are disclosed. The PLD includes an array of PLD cells. Each PLD cell may include a programmable transistor and a select transistor. The PLD array is divided into at least one first area and at least one second area adjacent the at least one first area. The at least one first area includes the programmable transistors and the at least one second area includes the select transistors.

Abstract translation: 公开了一种用于制造PLD的可编程逻辑器件（PLD）和方法。 PLD包括一系列PLD细胞。 每个PLD单元可以包括可编程晶体管和选择晶体管。 PLD阵列被分成至少一个第一区域和与该至少一个第一区域相邻的至少一个第二区域。 所述至少一个第一区域包括可编程晶体管，并且所述至少一个第二区域包括所述选择晶体管。

公开(公告)号：US20050030002A1

公开(公告)日：2005-02-10

申请号：US10637985

申请日：2003-08-08

Applicant: Jianwen Shao ,  Thomas Hopkins

Inventor： Jianwen Shao ,  Thomas Hopkins

IPC: H02P6/18 ,  H02P6/22 ,  G01R25/00

CPC classification number: H02P6/182 ,  H02P1/029 ,  H02P6/22

Abstract: A device and method that determine a freewheeling rotation of an electric motor. The method includes steps of measuring first and second signals from respective first and second windings of an unenergized motor, and determining from the first and second signals whether the unenergized motor is rotating. The method may also include determining from the first and second signals the direction of rotation if the unenergized motor is rotating. The method may further include measuring a third signal from a third winding of the unenergized motor, and determining whether the motor is rotating may include determining that the motor is not rotating if the first, second, and third signals are equal. The first and second signals may each comprise a respective back voltage.

Abstract translation: 确定电动机的续流旋转的装置和方法。 该方法包括以下步骤：测量来自未通电电动机的相应第一和第二绕组的第一和第二信号，以及从第一和第二信号确定未通电电动机是否正在旋转。 该方法还可以包括如果未通电的电动机正在旋转，则从第一和第二信号确定旋转方向。 该方法还可以包括测量来自未通电电动机的第三绕组的第三信号，并且确定电动机是否正在旋转可以包括如果第一，第二和第三信号相等则确定电动机不旋转。 第一和第二信号可以各自包括相应的反向电压。

公开(公告)号：US20050006670A1

公开(公告)日：2005-01-13

申请号：US10604318

申请日：2003-07-10

Applicant: Thomas Zounes

Inventor： Thomas Zounes

IPC: H01L27/02 ,  H01L27/10 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.

Abstract translation: 用于设计集成多米诺骨牌电路的单元库具有第一库部分，具有多个具有不同晶体管尺寸和/或逻辑功能的可选逻辑电路，用于根据期望的逻辑功能和参数特性进行选择。 第二库部分包括多个可选择的可预充电驱动器电路。 每个驱动器电路被配置为可连接到所选逻辑电路的输出端。 驱动器电路还具有至少不同的晶体管尺寸。 可以构造标准FET器件，以在多米诺逻辑电路的设计中对所选择的逻辑电路的输出节点进行预充电。

公开(公告)号：US06842092B2

公开(公告)日：2005-01-11

申请号：US09757378

申请日：2001-01-09

Applicant: James Brady ,  Duane Giles Laurent

Inventor： James Brady ,  Duane Giles Laurent

IPC: H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01P3/08

CPC classification number: H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors.

Abstract translation: 提供了一种装置和方法，其减少了将电信号从电路的第一区域传递到电路的第二区域的导体中的传播延迟。 导体被制造成包括从第一区域延伸到第二区域的第一导体。 导体还包括基本上平行且沿着第一导体延伸并电连接到第一导体的第二导体。 还可以使用第三和附加导体，其基本上平行延伸并且沿着第一导体延伸并且电连接到第一导体。 额外的第二导体（和任何附加导体）减小了导体的电容，从而减少了导体中的传播延迟（增加了信号的速度）。 附加导体有效地“屏蔽”第一导体不受第一导体通常“看到”的一些电容，而不使用这种附加导体。

公开(公告)号：US20050002144A1

公开(公告)日：2005-01-06

申请号：US10611043

申请日：2003-07-01

Applicant: Vineet Twari ,  Roberto Alini

Inventor： Vineet Twari ,  Roberto Alini

IPC: H03F3/345 ,  G11B5/00 ,  G11B5/012 ,  H03K17/0814 ,  H03K17/10 ,  H02H3/22

CPC classification number: H03K17/08142 ,  G11B5/012 ,  G11B2005/0013 ,  H03K17/102

Abstract: A driver circuit includes a CMOS stage and switch functionalities for performing certain tasks. One task is to selectively block exposure of the CMOS stage to reference voltage(s). Another task is to selectively protect the CMOS stage during transient operation. Yet another task is to block leakage current from flowing from the CMOS stage to ground.

Abstract translation: 驱动器电路包括用于执行某些任务的CMOS级和开关功能。 一个任务是选择性地阻止CMOS级的参考电压的暴露。 另一个任务是在瞬态操作期间选择性地保护CMOS级。 另一个任务是阻止漏电流从CMOS级流到地。