公开(公告)号：US5132866A

公开(公告)日：1992-07-21

申请号：US553455

申请日：1990-07-17

Applicant: Salvatore Raciti ,  Sergio Palara

Inventor： Salvatore Raciti ,  Sergio Palara

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/732

CPC classification number: H01L27/0248

Abstract: A monolithic integrated circuit (M) includes a power device (Q3, Q4) for driving an inductive load (L) and a control device for the power device. The control device comprises a voltage limiting circuit which includes a first transistor (Q2) responsive to negative impulses of the supply voltage and a second transistor (Q5) which is controlled by the first transistor for controlling re-firing of the power device in case of a negative pulse of the power voltage during a quenching period of the power device. The monolithic integrated circuit includes a substrate (5) having a substrate surface forming a supply voltage terminal of the power device and having a substrate voltage. An annular pocket (40) is formed in the substrate to surround or at least partially contain at least the first transistor (Q2) of the voltage limiting circuit. According to differing modes of the invention, the annular pocket (40) is biased at a voltage depending on that of the supply voltage terminal of the power device; is left at a floating potential. In one embodiment a pocket (3) is surrounded by an area of a different conductivity type (70) which has a grounded contact distributed along an emerging portion thereof.

公开(公告)号：US5113239A

公开(公告)日：1992-05-12

申请号：US583271

申请日：1990-09-17

Applicant: Carlo Cini ,  Angelo Massironi ,  Luigi Sisti

Inventor： Carlo Cini ,  Angelo Massironi ,  Luigi Sisti

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/49 ,  H01L23/495

CPC classification number: H01L24/85 ,  H01L23/49541 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49505 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

Abstract: An integrated device with improved connections between the pins and the semiconductor material chip which integrates electronic components. In order to allow the integration of signal components and power components in a same device with a reduced use of area for the soldering pads and with high reliability of the connections, the connecting wires are made of different materials. Advantageously, the wires for the power connections are based on aluminum and have large diameters, and the wires for the signal connections are gold-based and have a small diameter. In order to ensure good soldering, the ends of the pins on which the connecting wires are to be soldered are gold-plated.

公开(公告)号：US5103416A

公开(公告)日：1992-04-07

申请号：US439792

申请日：1989-11-21

Applicant: Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

Inventor： Franco Cavallotti ,  Alessandro Cremonesi ,  Rinaldo Poluzzi

IPC: H03H17/02 ,  H03H17/06

CPC classification number: H03H17/0607 ,  H03H17/02 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0692

Abstract: The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.

公开(公告)号：US5086299A

公开(公告)日：1992-02-04

申请号：US520724

申请日：1990-05-09

Applicant: Giulio Frigerio ,  Alessandro Cremonesi

Inventor： Giulio Frigerio ,  Alessandro Cremonesi

IPC: H03M1/14 ,  H03M1/36

CPC classification number: H03M1/144

Abstract: A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

公开(公告)号：US5072278A

公开(公告)日：1991-12-10

申请号：US480162

申请日：1990-02-14

Applicant: Mario Paparo ,  Sergio Palara

Inventor： Mario Paparo ,  Sergio Palara

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K5/02

CPC classification number: H01L27/0623

Abstract: The monolithic integrated structure comprises a semiconductor substrate, a superimposed first epitaxial stratum having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second isolation pocket which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum at a distance such as to define an interposed area of said first stratum capable of isolating said isolating pockets from one another. Within the latter pockets, there are provided respective embedded strata and superimposed regions of a second epitaxial stratum having characteristics such as to withstand the low voltage applied across the two driving stages. A further region of said second epitaxial stratum is superimposed over said area of said first epitaxial stratum. The above regions of isolation pockets are designed for the formation of two high and low voltage driving stages, while the above further region of the second epitaxial stratum may be used for the formation of a level translator circuit component. Means are provided for the protection of said circuit component against high supply voltages.

公开(公告)号：US5068202A

公开(公告)日：1991-11-26

申请号：US448883

申请日：1989-12-12

Applicant: Pier L. Crotti ,  Nadia Iazzi

Inventor： Pier L. Crotti ,  Nadia Iazzi

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/32 ,  H01L21/762

CPC classification number: H01L21/32 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/76237 ,  Y10S438/944 ,  Y10S438/978

Abstract: Encased (BOX) trench insolation structures in a silicon substrate are formed by firstly RIE etching an ONO multilayer (Oxide-Nitrite-Oxide) formed on the surface of a monocrystalline silicon substrate through a mask defining the active areas until exposing the silicon. A successive deposition of a conformable TEOS oxide layer followed by a "blanket" RIE etching, leave tapered "spacers" on the vertical etched flanks of the ONO multilayer. Through such a self-aligned "aperture" an isotropic plasma etching (round-etch) of the silicon is performed until the lateral, under-cut, etch front below the oxide spacers reaches the bottom layer of the isolation area defining etching previously conducted through the ONO multilayer. The peculiarities of the round-etch profile are thus fully exploited for more easily implanting the walls and bottom of the trench and avoiding the presence of electric field affecting sharp corners. The process maintains a precise lateral dimensional control and does not require special high resolution apparatuses.

公开(公告)号：US5065213A

公开(公告)日：1991-11-12

申请号：US288405

申请日：1988-12-21

Applicant: Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/0716 ,  Y10S148/009

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor an a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the first, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

公开(公告)号：US5061901A

公开(公告)日：1991-10-29

申请号：US515952

申请日：1990-04-27

Applicant: Germano Nicollini ,  Rinaldo Castello

Inventor： Germano Nicollini ,  Rinaldo Castello

IPC: H03F1/48 ,  H03F1/08 ,  H03F3/345 ,  H03F3/45

CPC classification number: H03F3/45179 ,  H03F1/086 ,  H03F3/45183 ,  H03F2203/45031 ,  H03F2203/45034 ,  H03F2203/45192 ,  H03F2203/45281 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03F2203/45658

Abstract: A circuit arrangement for increasing the gain-bandwidth product of a CMOS amplifier having a differential cell input stage comprises, within said input stage:a pair of active components having a characteristic function which corresponds with that of a negative value resistor, for increasing the transconductance of the stage,a pair of capacitors being each respectively associated with a corresponding one of the active components to introduce a pole/zero pair in the frequency response from the amplifier, andan additional input stage cross-connected to the differential cell for bringing the frequency value of the zero a predetermined distance away from the amplifier clipping frequency.

公开(公告)号：US5041885A

公开(公告)日：1991-08-20

申请号：US518070

申请日：1990-05-02

Applicant: Fabio Gualandris ,  Aldo Maggis

Inventor： Fabio Gualandris ,  Aldo Maggis

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/66636 ,  Y10S257/90

Abstract: A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.The modified fabrication steps are readily integrable in a normal CMOS fabrication process.

公开(公告)号：US5034800A

公开(公告)日：1991-07-23

申请号：US366840

申请日：1989-06-15

Applicant: Giuseppe Marchisi

Inventor： Giuseppe Marchisi

IPC: H01L23/31

CPC classification number: H01L23/315 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247

Abstract: A hollow-type package of optically and non-optically active semiconductor devices is entirely made of moldable plastic material by utilizing a preformed box-like shell of a rigid plastic material for enclosing the semiconductor dye and the electrical connection wires before molding the shell in an epoxy resin. The protective shell is composed of two corresponding half parts and, in the case of optically active devices, the top half of the shell is provided with a window closed by a transparent pane which is sealed during the encapsulation. Preferably, the two halves of the protection shell have two spaced lateral walls forming two spaced sealing perimeters and a perimetral chamber which is formed therebetween and surrounds a central cavity of the shell for accommodating any encapsulating resin which may eventually enter through the outer sealing perimeter during molding. The central cavity of the shell may be filled with a nonrigid silicon resin before molding for further increasing the protection. The entirely plastic hollow package may be formed through a normal plastic molding process.