公开(公告)号：US20200303414A1

公开(公告)日：2020-09-24

申请号：US16894624

申请日：2020-06-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/768

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20200258903A1

公开(公告)日：2020-08-13

申请号：US16792790

申请日：2020-02-17

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L23/00 ,  H01L21/768

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

公开(公告)号：US20200227123A1

公开(公告)日：2020-07-16

申请号：US16744067

申请日：2020-01-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  Robert D. Normal ,  Eli Harari

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792

Abstract: NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

公开(公告)号：US20200219572A1

公开(公告)日：2020-07-09

申请号：US16820209

申请日：2020-03-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as 3-dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

公开(公告)号：US10593698B2

公开(公告)日：2020-03-17

申请号：US16593642

申请日：2019-10-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C11/00 ,  H01L27/11582 ,  H01L29/10 ,  G11C16/04 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/522 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/786 ,  H01L23/528 ,  H01L29/06

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US10475812B2

公开(公告)日：2019-11-12

申请号：US16447406

申请日：2019-06-20

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C11/00 ,  H01L27/11582 ,  H01L29/06 ,  G11C16/04 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/522 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/786 ,  H01L23/528 ,  H01L29/10

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20190244971A1

公开(公告)日：2019-08-08

申请号：US16252301

申请日：2019-01-18

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L29/786 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/30 ,  G11C16/14 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/78642

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20190157296A1

公开(公告)日：2019-05-23

申请号：US16194225

申请日：2018-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  George Samachisa ,  Yupin Fong

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/423

Abstract: A non-volatile “reverse memory cell” suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

公开(公告)号：US12245430B2

公开(公告)日：2025-03-04

申请号：US18223994

申请日：2023-07-19

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Tianhong Yan

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

公开(公告)号：US20250024685A1

公开(公告)日：2025-01-16

申请号：US18755360

申请日：2024-06-26

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Jie Zhou ,  Christopher J. Petti ,  Eli Harari ,  Kavita Shah

IPC: H10B51/20 ,  G11C5/06 ,  G11C16/04 ,  G11C16/14 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10

Abstract: A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.