公开(公告)号：US20150180425A1

公开(公告)日：2015-06-25

申请号：US14139672

申请日：2013-12-23

Applicant: Analog Devices Technology

Inventor： Dzianis Lukashevich

IPC: H03F1/30

CPC classification number: H03F1/30 ,  H01L27/1203 ,  H03F2200/447 ,  H03F2200/468 ,  H03F2200/528

Abstract: This disclosure relates to temperature stabilization of at least a portion of an amplifier, such as a logarithmic amplifier, and/or a band gap reference circuit. In one aspect, one or more stages of an amplifier, a heater, and a temperature sensor are included in a semiconductor material and surrounded by thermally insulating sidewalls.

Abstract translation: 本公开涉及放大器，例如对数放大器和/或带隙基准电路的至少一部分的温度稳定。 在一个方面，放大器，加热器和温度传感器的一个或多个级包括在半导体材料中并被隔热侧壁包围。

公开(公告)号：US09054731B2

公开(公告)日：2015-06-09

申请号：US14073396

申请日：2013-11-06

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： David Nelson Alldred ,  Jipeng Li ,  Richard E. Schreier ,  Hajime Shibata

IPC: H03M3/00 ,  H03M1/18

CPC classification number: H03M3/442 ,  H03M3/43 ,  H03M3/454

Abstract: In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.

Abstract translation: 在一个示例实现中，本公开提供了一种在连续时间Σ-Δ模数转换器中使用的环路滤波器。 具体地，在一系列运算放大器积分器中的第一运算放大器的输入处提供电容反馈数模转换器路径。 在第一运算放大器的输入处的电容反馈数模转换器减少了第一运算放大器的输出处的信号内容，从而减小了第一运算放大器的输出摆幅。 输出摆幅的减小提供了更有效的环路滤波器。

公开(公告)号：US20150115923A1

公开(公告)日：2015-04-30

申请号：US14064490

申请日：2013-10-28

Applicant: Analog Devices Technology

Inventor： Bin Shao

IPC: H02M3/158 ,  H02M3/157

CPC classification number: H02M3/158 ,  H02M3/157 ,  H02M2001/0009

Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.

Abstract translation: 开关调节器或其他装置或技术可以包括负载电流监视以提供估计负载电流的数字表示。 负载电流监视可以由包括计数器电路，比较器电路和耦合到计数器电路的数字控制源的电路执行，并且被配置为响应于由计数器电路提供的计数来调整感测装置的偏置条件 以便建立由感测装置传导的电流与由电力开关装置传导的对应电流之间的比例关系。 计数器电路被配置为响应于由比较器输出提供的信息而增加和减少计数，并且计数通常表示估计的负载电流，例如平均负载电流。

公开(公告)号：US20150109157A1

公开(公告)日：2015-04-23

申请号：US14055980

申请日：2013-10-17

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Trevor Clifford Caldwell ,  Richard E. Schreier

IPC: H03M3/00

CPC classification number: H03M3/458 ,  G01R19/25 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30

Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.

Abstract translation: Δ-Σ调制器被配置为感测并将电磁场转换成数字信号。 示例性的Δ-Σ调制器包括诸如LC谐振器的传感器组件，其被配置为感测电磁场并产生输入模拟信号，其中Δ-Σ调制器被配置为将输入的模拟信号转换为数字信号 。 Δ-Σ调制器可以包括耦合到传感器组件的模数转换器，其接收并将输入的模拟信号转换成数字信号。 Δ-Σ调制器还可以包括耦合到谐振器和ADC的数模转换器（DAC），DAC被配置为从ADC接收数字信号并产生反馈模拟信号。

公开(公告)号：US08947446B2

公开(公告)日：2015-02-03

申请号：US13892531

申请日：2013-05-13

Applicant: Analog Devices Technology

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06F13/372 ,  G06K9/36 ,  G06K9/64 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，即使当处理操作转换到新的像素像素或一行像素时，仍然保持恒定的提取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US20150030250A1

公开(公告)日：2015-01-29

申请号：US13951193

申请日：2013-07-25

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bijesh Poyil ,  Ramandeep Singh Kukreja ,  Anil M. Sripadarao

IPC: G06K9/48

CPC classification number: G06K9/48 ,  G06K9/4638 ,  G06T7/11 ,  G06T7/12 ,  G06T7/13 ,  G06T7/136 ,  G06T7/181 ,  G06T7/194 ,  G06T2200/28

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract translation: 一种方法包括确定像素图的一行中的非零运行的位置和长度。 该方法还包括至少部分地基于位置和长度来确定前一行中的非零运行的数量的邻居。 另外，该方法至少部分地基于非零运行的第二邻居的对应关系图来更新非零运行的对应关系图和非零运行的第一邻居的对应关系图 响应于确定非零运行在前一行中具有至少两个邻居。

公开(公告)号：US08860598B2

公开(公告)日：2014-10-14

申请号：US13839972

申请日：2013-03-15

Applicant: Analog Devices Technology

Inventor： Frederick Carnegie Thompson ,  John Cullinane

IPC: H03M1/60 ,  H03M1/14

CPC classification number: H03M1/145 ,  H03M1/36 ,  H03M1/46

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract translation: A转换器系统，包括对输入信号的第一部分进行数字化的第一转换器，第一转换器包括比较器，具有模拟第一转换器中的比较器的电路结构的电路结构的定时器，定时器接收输入 信号，其指示比较器中的操作开始;第二转换器，响应于来自定时器的输出，数字化从第一部分剩余的输入信号的第二部分;以及组合器，具有从第一数字化生成数字代码的输入， 第二部分。

公开(公告)号：US20140285249A1

公开(公告)日：2014-09-25

申请号：US13848929

申请日：2013-03-22

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Eberhard Brunner

IPC: G01R19/02

CPC classification number: G01R19/02

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.

Abstract translation: 均方根（RMS）检测器包括检测电路，其具有作为输入的射频信号，目标电压和设定电压以及RMS信号作为输出，以及检测电路内的增益级，以产生RMS信号作为 一个输出。 增益级提供检测器更快的建立时间。

公开(公告)号：US20140282349A1

公开(公告)日：2014-09-18

申请号：US14028792

申请日：2013-09-17

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Roger Feng ,  Junxiao Chen ,  Bin Shao

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F2217/78

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract translation: 一种方法可以在从引脚解复用（解调））电压时重用至少一个引脚。 该方法可用于在测试（DFT）相位的设计中设置精确的电流限制阈值，从而准确地设置限流器的修整代码。 该方法使用功率MOSFET在大漏极电流下具有几乎相同的导电电阻的性质。 因此，可以根据小于ATE能够提供的最大电流的小电流宿的准确的漏极 - 源极电压Vds来设置电流限制阈值。 可以通过连接到电流检测电路的功率MOSFET的开尔文感测漏极和源极引脚来测量精确的电压Vds。

公开(公告)号：US20140266377A1

公开(公告)日：2014-09-18

申请号：US14162297

申请日：2014-01-23

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Kareem Atout

IPC: H03K3/011

CPC classification number: H03K3/011 ,  H02M3/157 ,  H02M2001/008

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract translation: 在一个示例中，公开了一种用于电源的混合模拟 - 数字点负载控制器（ADPOL）。 ADPOL配置为响应瞬态电流负载。 在存在中等电流瞬变的情况下，功率由数字电源核心计时，数字电源核心可以被编程配置为响应于瞬态来调整脉冲宽度。 在存在较大的电流瞬变的情况下，可以将控制传递到模拟瞬态补偿器，其包括在非常高占空比时钟和非常低占空比时钟之间的高速电路选择，这将驱动瞬态回 到数字控制领域。