公开(公告)号：US07240581B2

公开(公告)日：2007-07-10

申请号：US10911724

申请日：2004-08-04

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G05G1/14 ,  B60K28/10 ,  B60D1/28

CPC classification number: G05G1/30 ,  G05G1/327 ,  G05G1/60 ,  Y10T74/20528 ,  Y10T74/20888

Abstract: An installation structure releases a brake pedal in a vehicle collision. A pedal arm has a groove coupled with a pipe. A front portion of the groove has a smaller width than the pipe. Alternatively, a pedal arm is hingedly mounted on a support member. A connector secures the pedal arm to the support member for normal operation, and permits separation of the pedal arm from the support member in response to a reward force resulting from a collision impact. The support member has a cylindrical member, and the pedal arm defines a forward facing opening, force-fit onto the cylindrical member. The opening has a width smaller than the cylindrical member. Alternatively, the connector has two support plates on a pipe of the cylindrical member, at both sides of the pedal arm. The plates have rear-facing grooves, and coupling members protruding from the pedal arm are received in the grooves.

Abstract translation: 安装结构在车辆碰撞中释放制动踏板。 踏板臂具有与管道连接的凹槽。 槽的前部具有比管更小的宽度。 或者，踏板臂铰接地安装在支撑构件上。 连接器将踏板臂固定到支撑构件以进行正常操作，并且允许踏板臂与支撑构件响应于碰撞冲击产生的奖励力而分离。 支撑构件具有圆柱形构件，并且踏板臂限定向前的开口，并将其压配合到圆柱形构件上。 开口的宽度比圆柱形件小。 或者，连接器在踏板臂的两侧在圆柱形构件的管道上具有两个支撑板。 这些板具有后置凹槽，并且从踏板臂突出的联接构件容纳在凹槽中。

公开(公告)号：US20060180851A1

公开(公告)日：2006-08-17

申请号：US11402389

申请日：2006-04-12

Applicant: Chang-Hyun Lee ,  Jung-Dal Choi

Inventor： Chang-Hyun Lee ,  Jung-Dal Choi

IPC: H01L29/788

CPC classification number: G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7782 ,  H01L29/792 ,  H01L29/7923

Abstract: Non-volatile memory devices and methods of operating the same are disclosed. A non-volatile memory device includes a semiconductor substrate. A tunnel insulating layer and a gate electrode are on the semiconductor substrate. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with a plurality of layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than a minimum field in the blocking insulation layer. A minimum field established at a blocking insulation layer can be stronger than a minimum field established at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than that of charges through the blocking insulation layer. Therefore, it may be possible to use lower operation voltages, obtain higher program and erase speeds, and/or obtain a greater difference between threshold values of a program threshold voltage and an erase threshold voltage. As a result, a multi-valued non-volatile memory device may be formed therefrom.

Abstract translation: 公开了非易失性存储器件及其操作方法。 非易失性存储器件包括半导体衬底。 隧道绝缘层和栅电极位于半导体衬底上。 具有多个层的多重隧道绝缘层，电荷存储绝缘层和具有多个层的多重阻挡绝缘层依次堆叠在栅电极和隧道绝缘层之间。 半导体衬底中的第一扩散区域和第二扩散区域与栅电极的相对的相对侧相邻。 当向栅电极和半导体衬底施加电压以形成其间的电压电平差时，隧道绝缘层中的最小场强比阻挡绝缘层中的最小场强。 在阻挡绝缘层处建立的最小场强可以比在隧道绝缘层处建立的最小场强更强，并且通过隧道绝缘层的电荷的迁移概率可以高于通过阻挡绝缘层的电荷的迁移概率。 因此，可以使用较低的操作电压，获得更高的编程和擦除速度，和/或获得程序阈值电压和擦除阈值电压的阈值之间的较大差异。 结果，可以从其形成多值非易失性存储器件。

公开(公告)号：US07081651B2

公开(公告)日：2006-07-25

申请号：US10186153

申请日：2002-06-27

Applicant: Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

Inventor： Jung-Dal Choi ,  Jong-Woo Park ,  Seong-Soon Cho ,  Chang-Hyun Lee

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

Abstract translation: 非易失性存储器件包括顺序层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

公开(公告)号：USD513952S1

公开(公告)日：2006-01-31

申请号：US29190443

申请日：2003-09-18

Applicant: Chang Hyun Lee ,  In Seok Choi

Designer： Chang Hyun Lee ,  In Seok Choi

公开(公告)号：US20050237783A1

公开(公告)日：2005-10-27

申请号：US11128038

申请日：2005-05-12

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/792 ,  G11C11/22

CPC classification number: G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

公开(公告)号：US06903406B2

公开(公告)日：2005-06-07

申请号：US10346957

申请日：2003-01-17

Applicant: Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

Inventor： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

Abstract translation: 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US06894924B2

公开(公告)日：2005-05-17

申请号：US10133684

申请日：2002-04-25

Applicant: Jung-Dal Choi ,  Chang-Hyun Lee

Inventor： Jung-Dal Choi ,  Chang-Hyun Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program voltage higher than 0 volts and a ground voltage to a gate electrode and a channel region of a selected SONOS cell transistor, respectively. Also, an erasing operation is accomplished by applying a ground voltage and a first erase voltage lower than 0 volts to a bulk region and a gate electrode of a selected SONOS cell transistor, respectively, and by applying a second erasure voltage to either a drain region or a source region of the selected SONOS cell transistor. The second erase voltage is a ground voltage or a positive voltage. In addition, a read operation is accomplished using either a backward read mode or a forward read mode. Thus, it is possible to remarkably improve a bake retention characteristic, which is sensitive to a thickness of the tunnel oxide layer.

Abstract translation: 提供了一种编程，擦除和读取具有大于20埃的隧道氧化物层的氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储器件的操作方法。 该方法的程序操作通过分别向所选择的SONOS单元晶体管的栅电极和沟道区施加高于0伏的编程电压和接地电压来实现。 此外，擦除操作是通过分别对所选择的SONOS单元晶体管的体区域和栅电极施加接地电压和低于0伏特的第一擦除电压来实现的，并且通过向漏极区域施加第二擦除电压 或所选择的SONOS单元晶体管的源极区域。 第二擦除电压是接地电压或正电压。 此外，使用反向读取模式或正向读取模式来实现读取操作。 因此，可以显着提高对隧道氧化物层的厚度敏感的烘烤保持特性。

公开(公告)号：US06336376B1

公开(公告)日：2002-01-08

申请号：US09419713

申请日：1999-10-14

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G05G114

CPC classification number: G05G1/32 ,  B60T7/065 ,  Y10T74/20528 ,  Y10T74/2063

Abstract: A brake pedal supporting structure designed for a brake pedal of a car having a pedal arm coupled with a mounting bracket attached to a dash panel and a cowl panel to rotate via an actuating rod and a hinge point of a brake booster, wherein pedal arm pushing preventing means is fixed at the rear portion of the pedal arm to face a predetermined interval of the total length of the pedal arm including the hinge point to prevent the pedal arm from being pushed to the rear by the brake booster which will be pushed toward the inside of the car room at the time of a head-on colliding car crash, thereby keeping the pedal arm from being pushed toward the rear of the chassis or enabling the lower portion of the pedal arm to rotate to the front of the chassis to rule out an impact given by the pedal arm onto the driver's lower body and reduce the possibility of the injury at the time of the head-on colliding car crash.

Abstract translation: 一种制动踏板支撑结构，其设计用于汽车的制动踏板，该制动踏板具有踏板臂，该踏板臂与连接到仪表板上的安装支架连接，并且前罩板经由致动杆和制动助力器的铰接点旋转，其中踏板臂推动 防止装置固定在踏板臂的后部以面对包括铰链点的踏板臂的总长度的预定间隔，以防止踏板臂被制动助力器推向后方，该制动助力器将被推向 在碰撞碰撞时，汽车内部的内部，从而保持踏板臂不被推向底盘的后部，或使踏板臂的下部旋转到底盘的前面以规定 将踏板臂施加到驾驶员的下身上，并减少在碰撞碰撞时发生伤害的可能性。

公开(公告)号：US06299522B1

公开(公告)日：2001-10-09

申请号：US09460637

申请日：1999-12-14

Applicant: Chang Hyun Lee

Inventor： Chang Hyun Lee

IPC: B23F2103

CPC classification number: B24B55/102 ,  B24D7/06

Abstract: A grinding wheel having dust discharge-impelling blades which are able to impel to discharge the dust produced during the grinding operation to a dust collection machine to decrease dispersing dust in the air, and increase the cooling efficiency of the grinding wheel to enhance the grinding ability and the life of the grinding wheel. The grinding wheel of the present invention comprises a shank for connecting with a shaft of electric motor, having a plurality of dust discharging holes disposed at given intervals in the shank and a plurality of dust discharge-impelling blades disposed between the dust discharging holes for impelling to discharge dust produced during the grinding operation through and in cooperation with dust discharging holes, and a plurality of grinding tips disposed fixedly at predetermined intervals on the lower surface of the circumferential portion of the shank by means of welding or joining.

Abstract translation: 具有能够促进粉碎操作时产生的粉尘向灰尘收集机排出的粉尘排出推动叶片的砂轮，以减少空气中的分散灰尘，提高砂轮的冷却效率，提高研磨能力 砂轮的寿命。本发明的砂轮包括用于与电动机的轴连接的柄，具有以规定间隔设置在柄中的多个灰尘排放孔和多个排尘推进叶片 设置在用于推动的粉尘排放孔之间并与粉尘排放孔协同地排放在研磨操作期间产生的灰尘;以及多个研磨尖，其以预定间隔固定地设置在柄的圆周部分的下表面上，借助于 焊接或接合。

公开(公告)号：US5810930A

公开(公告)日：1998-09-22

申请号：US613617

申请日：1996-03-11

Applicant: Young Chang Eom ,  In Ho Hwang ,  Koeng Su Lim ,  Chang Hyun Lee

Inventor： Young Chang Eom ,  In Ho Hwang ,  Koeng Su Lim ,  Chang Hyun Lee

IPC: C30B35/00 ,  C23C16/48 ,  C30B25/00 ,  H01L21/205 ,  H01L21/31 ,  C23C16/00

CPC classification number: C23C16/48

Abstract: A photo-chemical vapor deposition ("photo-CVD") apparatus has exchange apparatus of optical window and method of exchanging optical window therewith. There photo-CVD apparatus has exchange apparatus of optical window which can replace an optical window blurred by attachment of materials produced by dissociation of reaction gas or materials used for disposition in a reaction chamber of a photo-CVD apparatus during photo-CVD reaction with a clean optical window without exposing the inside of the reaction chamber to the air and to the method of exchanging optical window of the photo-CVD apparatus using the exchange apparatus of optical window.

Abstract translation: 光化学气相沉积（“photo-CVD”）装置具有光学窗口的交换装置和与其交换光学窗口的方法。 光刻CVD装置具有光学窗口的交换装置，该光学窗口可以通过将光反应室中的反应气体或用于配置的材料通过解离而产生的材料与光CVD反应中的光CVD 清洁光学窗口，而不会将反应室内部暴露在空气中，以及使用光学窗口的交换装置更换光CVD装置的光学窗口的方法。