公开(公告)号：US20090114949A1

公开(公告)日：2009-05-07

申请号：US11934040

申请日：2007-11-01

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66734

Abstract: High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.

Abstract translation: 公开了高迁移率垂直沟槽DMOSFET及其制造方法。 高迁移率垂直沟槽DMOSFET的源极区，漏极区或沟道区可以包括增加沟道区中电荷载流子迁移率的硅锗（SiGe）。 在一些实施例中，通道区域可能被应变以增加沟道电荷载流子迁移率。

公开(公告)号：US07504676B2

公开(公告)日：2009-03-17

申请号：US11444853

申请日：2006-05-31

Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

IPC: H01L29/80

CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

公开(公告)号：US20090020843A1

公开(公告)日：2009-01-22

申请号：US11880497

申请日：2007-07-22

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/47 ,  H01L21/44

CPC classification number: H01L29/872 ,  H01L29/402 ,  H01L29/66143 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as an Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.

公开(公告)号：US20080024102A1

公开(公告)日：2008-01-31

申请号：US11830996

申请日：2007-07-31

Applicant: Francois Hebert ,  Allen Chang

Inventor： Francois Hebert ,  Allen Chang

IPC: G05F1/618

CPC classification number: H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract translation: 提出了具有由功率调节控制器（PRC）控制的输出电感器，低侧肖特基二极管和高侧垂直MOSFET的多管芯封装中的DC-DC降压转换器。 多管芯封装包括第一管芯焊盘，肖特基二极管与垂直MOSFET并排放置在其上。 PRC管芯通过绝缘管芯接合连接在第一管芯焊盘顶上。 或者，第一管芯焊盘接地。 垂直MOSFET是顶漏N沟道FET，肖特基二极管管芯的基极是其阳极。 肖特基二极管和垂直MOSFET堆叠在第一芯片焊盘的顶部。 PRC通过导电芯片键连接在第一裸片焊盘顶上。 肖特基二极管管芯可以以倒装芯片的形式提供，阴极是其衬底。 或者，肖特基二极管被提供有阳极作为其衬底而没有倒装芯片配置。

公开(公告)号：US20060104004A1

公开(公告)日：2006-05-18

申请号：US11270874

申请日：2005-11-08

Applicant: Richard Harris ,  Stephen Coates ,  Francois Hebert

Inventor： Richard Harris ,  Stephen Coates ,  Francois Hebert

IPC: H02H1/00

CPC classification number: H02H9/025 ,  H02H5/042 ,  H02H5/044

Abstract: An apparatus and method for temperature-dependent transient blocking employing a transient blocking unit (TBU) that uses at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device. The interconnection is performed such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert to effectuate their mutual switch off to block the transient. The apparatus has a temperature control unit that is in communication with the TBU and adjusts at least one of the bias voltages Vp, Vn in response to a sensed temperature Ts, thereby enabling the apparatus to also respond to over-temperature. In some embodiments the p-channel device is replaced with a positive temperature coefficient thermistor (PTC). The temperature control unit can use any suitable circuit element, including, among other a PTC, resistor, negative temperature coefficient element, positive temperature coefficient element, transistor, diode.

Abstract translation: 一种采用使用与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）的温度依赖性瞬态阻塞的装置和方法。 执行互连，使得瞬态改变p沟道器件的偏置电压V SUB p N和N沟道器件的偏置电压V N n N一致地实现 他们的相互关闭来阻止瞬态。 该装置具有与TBU通信的温度控制单元，并响应于感测到的温度T 1调整至少一个偏置电压V SUB，V SUB， 从而使得设备也能够响应过温。 在一些实施例中，用正温度系数热敏电阻（PTC）代替p沟道器件。 温度控制单元可以使用任何合适的电路元件，包括PTC，电阻器，负温度系数元件，正温度系数元件，晶体管，二极管等。

公开(公告)号：US06989309B2

公开(公告)日：2006-01-24

申请号：US10858619

申请日：2004-06-01

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L31/113

CPC classification number: H01L21/26513 ,  H01L21/2658 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/7833

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. Particularly, a P-type dopant may diffuse farther up into an epitaxial layer than an N-type dopant to form an up-retro well.

Abstract translation: 提供与低电压，亚微米CMOS和BiCMOS工艺兼容的高压MOS晶体管。 本发明的高压晶体管在形成外延层之前具有注入到衬底中的掺杂剂。 在形成外延层和随后的加热步骤期间，注入的掺杂剂从衬底扩散到外延层中。 注入的掺杂剂增加外延层下部的掺杂浓度。 注入的掺杂剂可以将掺杂剂扩散到外延层中，而不是掩埋层中的掺杂剂形成一个向上复古的阱，从而防止在高工作电压下对于薄的外延层进行垂直穿透。 特别地，P型掺杂剂可以比N型掺杂剂更深地扩散到外延层中以形成向上复古的阱。

公开(公告)号：US20060003511A1

公开(公告)日：2006-01-05

申请号：US10880527

申请日：2004-07-01

Applicant: Francois Hebert ,  Salman Ahsan

Inventor： Francois Hebert ,  Salman Ahsan

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/823462 ,  Y10S438/981

Abstract: The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gate oxide layers with intermediate etching to remove the deposited oxide from active regions wherein transistors with relatively thinner gate oxides are to be formed, and then implementing one or more thermal oxidation steps. Embodiments include forming semiconductor devices comprising transistors with two different gate oxide thicknesses by initially depositing an oxide film, selectively removing the deposited oxide film from active areas in which low voltage transistors having a relatively thin gate oxide are to be formed, and then implementing thermal oxidation.

Abstract translation: 通过将栅极氧化物层的厚度调整到特定的工作电压来优化各种晶体管的单独性能。 实施例包括通过初始沉积具有中间蚀刻的一个或多个栅极氧化物层来形成具有不同栅极氧化物厚度的晶体管，以从其中将形成具有相对更薄的栅极氧化物的晶体管去除沉积的氧化物，然后实施一个或多个热氧化步骤 。 实施例包括通过初始沉积氧化膜来形成包括具有两种不同栅极氧化物厚度的晶体管的半导体器件，从其中将形成具有相对薄的栅极氧化物的低压晶体管的有源区选择性地去除沉积的氧化物膜，然后实施热氧化 。

公开(公告)号：US06888207B1

公开(公告)日：2005-05-03

申请号：US10683922

申请日：2003-10-10

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/72

CPC classification number: H01L29/66659 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.

Abstract translation: 提供具有高击穿电压的高压晶体管。 这些高压晶体管形成有渐变漏极延伸区域。 电荷载流子的浓度越过每个漏极延伸区域越远离栅极，导致严重的电场移动离开栅极。 本发明的方法和结构可用于将晶体管的击穿电压增加到器件的理论极限。 具有分级扩展区域的高压晶体管可以是p沟道或n沟道MOSFET。

公开(公告)号：US06222229B1

公开(公告)日：2001-04-24

申请号：US09333123

申请日：1999-06-14

Applicant: Francois Hebert ,  Szehim Ng

Inventor： Francois Hebert ,  Szehim Ng

IPC: H01L2976

CPC classification number: H01L29/402 ,  H01L29/0692 ,  H01L29/7835

Abstract: A high frequency power field effect transistor has a self-aligned gate-drain shield adjacent to the gate and overlying the drain. Fabrication of the structure does not require complex or costly processing and the resulting self-aligned shield structure minimizes increase to input and output capacitances. Hot carrier injection and related shifts are reduced thereby improving reliability of the transistor.

Abstract translation: 高频功率场效应晶体管具有邻近栅极并覆盖漏极的自对准栅 - 漏屏蔽。 结构的制造不需要复杂或昂贵的处理，并且由此产生的自对准屏蔽结构使输入和输出电容的增加最小化。 热载流子注入和相关位移减小，从而提高晶体管的可靠性。

公开(公告)号：US06201444B1

公开(公告)日：2001-03-13

申请号：US09388295

申请日：1999-09-01

Applicant: John F. Sevic ,  Francois Hebert

Inventor： John F. Sevic ,  Francois Hebert

IPC: H03F304

CPC classification number: H03F1/301

Abstract: A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the current mirror transistor is modified whereby the drain-to-gate voltage can be positive, and the lightly doped drain region in the lateral n-channel reference transistor is shortened and dopant concentration increased to increase the electric field of the reference transistor to provide the hot carrier injection degradation characteristics similar to the main transistor. Additionally, the gate length of the reference transistor can be shortened to effect the hot carrier injection degradation.

Abstract translation: 修改用于RF放大器晶体管的电流镜偏置电路，由此电流镜的参考晶体管跟踪RF晶体管中的热载流子劣化。 对电流镜晶体管的栅极偏置被修改，从而漏极 - 栅极电压可以是正的，并且横向n沟道参考晶体管中的轻掺杂漏极区域被缩短并且掺杂剂浓度增加以增加参考晶体管的电场 提供类似于主晶体管的热载流子注入降解特性。 此外，可以缩短参考晶体管的栅极长度，以实现热载流子注入降级。