公开(公告)号：US20240377583A1

公开(公告)日：2024-11-14

申请号：US18196796

申请日：2023-05-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.

公开(公告)号：US12142686B2

公开(公告)日：2024-11-12

申请号：US17330780

申请日：2021-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Uzma Rana ,  Steven M. Shank ,  Mark D. Levy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

公开(公告)号：US20240369760A1

公开(公告)日：2024-11-07

申请号：US18141753

申请日：2023-05-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arpan Dasgupta ,  Zahidur Chowdhury ,  Takako Hirokawa ,  Vaishnavi Karra ,  Norman Robson

IPC: G02B6/12 ,  G02B6/136 ,  H04N5/33

Abstract: Structures including a light source and an edge coupler, and methods of forming and using such structures. The structure comprises a semiconductor substrate and a back-end-of-line stack on the semiconductor substrate. The back-end-of-line stack includes a first dielectric layer, a first plurality of metal features in the first dielectric layer, a second dielectric layer on the first dielectric layer, and a second plurality of metal features in the second dielectric layer. The second plurality of metal features have a non-overlapping relationship with the first plurality of metal features. The structure further comprises an edge coupler adjacent to the first plurality of metal features and the second plurality of metal features.

公开(公告)号：US20240361545A1

公开(公告)日：2024-10-31

申请号：US18307151

申请日：2023-04-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Erdem Kaltalioglu

IPC: G02B6/42

CPC classification number: G02B6/4248 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/564

Abstract: A structure includes an integrated circuit (IC) chip including a substrate. An input/output (I/O) opening extends inwardly from an exterior surface of the IC chip. A metal finger structure protrudes partly into the I/O opening, and outer surfaces of the metal finger structure are covered by a moisture barrier. The metal finger structure may provide stress-relief by removing attacking surfaces for stress in the I/O opening and/or otherwise reduces stress, such as film stresses, to reduce damage to the moisture barrier and improve reliability compared to conventional devices.

公开(公告)号：US12132080B2

公开(公告)日：2024-10-29

申请号：US17452651

申请日：2021-10-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Wenjun Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/0696 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/785

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

公开(公告)号：US12125530B2

公开(公告)日：2024-10-22

申请号：US18045524

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C13/00 ,  G11C11/16 ,  G11C27/02

CPC classification number: G11C13/0026 ,  G11C11/1655 ,  G11C13/0004 ,  G11C13/0038 ,  G11C27/02

Abstract: A structure for in-memory pipeline processing includes a memory bank array. Each bank includes single resistor or dual resistor memory elements connected between input nodes, respectively, and bitline(s) (e.g., a single bitline for a single resistor memory element and first and second bitlines for a dual resistor memory element). A feedback buffer is connected to each bitline and a corresponding output node in each bank and a column interconnect line connects corresponding output nodes of all banks in the same column. The initial bank in each row includes amplifiers connected between the input nodes and memory elements and track-and-hold devices (THs) connected to the input nodes to facilitate pipeline processing. Outputs of the amplifiers are also connected by row interconnect lines to memory elements in downstream banks in the same row. Optionally, voltage buffers are connected to row interconnect lines and integrated into at least some banks.

公开(公告)号：US20240348005A1

公开(公告)日：2024-10-17

申请号：US18134068

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Yusheng Bian ,  Koushik Ramachandran

IPC: H01S5/024 ,  G02B6/42 ,  H01S5/02345 ,  H01S5/0236 ,  H01S5/0237 ,  H01S5/183

CPC classification number: H01S5/02469 ,  G02B6/4215 ,  H01S5/02345 ,  H01S5/0236 ,  H01S5/0237 ,  H01S5/18305

Abstract: Structures including a photonics chip and a surface-mounted laser chip, and methods of forming same. The structure comprises a photonics chip including a surface, a laser chip including a light output and a body that are spaced from the surface of the photonics chip, a first adhesive between the body of the laser chip and the surface of the photonics chip, and a second adhesive between the body of the laser chip and the surface of the photonics chip. The light output is oriented toward the surface of the photonics chip, the first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity that is less than the first thermal conductivity of the first adhesive, and the second adhesive is disposed in a light path between the light output of the laser chip and the surface of the photonics chip.

公开(公告)号：US12113070B2

公开(公告)日：2024-10-08

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US20240329308A1

公开(公告)日：2024-10-03

申请号：US18127220

申请日：2023-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arpan Dasgupta ,  Yusheng Bian ,  John M. Safran ,  Norman Robson

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13

Abstract: Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.

公开(公告)号：US12107083B2

公开(公告)日：2024-10-01

申请号：US18462779

申请日：2023-09-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Meng Miao ,  Alain F. Loiseau ,  Souvick Mitra ,  You Li ,  Wei Liang

IPC: H01L27/02 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/0259 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/0288 ,  H01L27/1207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.