公开(公告)号：US08625381B2

公开(公告)日：2014-01-07

申请号：US13026460

申请日：2011-02-14

Applicant: Ho-Cheol Lee

Inventor： Ho-Cheol Lee

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  G11C8/02 ,  G11C8/12 ,  G11C8/10

CPC classification number: H01L23/544 ,  H01L24/04 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Abstract translation: 提供了包括n个堆叠芯片的堆叠半导体器件。 每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。 上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。 通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

公开(公告)号：US20120008513A1

公开(公告)日：2012-01-12

申请号：US13178820

申请日：2011-07-08

Applicant: Seung Min BAEK ,  Sang Ig RHO ,  Ho Cheol LEE ,  Jong Hun KIM ,  Jae Jin KIM

Inventor： Seung Min BAEK ,  Sang Ig RHO ,  Ho Cheol LEE ,  Jong Hun KIM ,  Jae Jin KIM

IPC: H04W24/00 ,  H04L12/26

CPC classification number: H04L43/028 ,  H04L43/026

Abstract: An apparatus and method for detecting a target flow in a wireless communication system are provided. The target flow detection method includes receiving a packet, determining a behavior state of the packet, comparing the behavior state with a plurality of stored behavior signatures, retrieving, when the behavior state matches one of the stored behavior signatures, a target flow corresponding to the behavior signature, and instructing a packet processor to process the target flow.

Abstract translation: 提供一种用于在无线通信系统中检测目标流的装置和方法。 目标流检测方法包括接收分组，确定分组的行为状态，将行为状态与多个存储的行为签名进行比较，当行为状态与所存储的行为签名中的一个匹配时，检索对应于 行为签名，并指示数据包处理器处理目标流。

公开(公告)号：US20110260331A1

公开(公告)日：2011-10-27

申请号：US13026460

申请日：2011-02-14

Applicant: Ho-Cheol LEE

Inventor： Ho-Cheol LEE

IPC: H01L23/48

CPC classification number: H01L23/544 ,  H01L24/04 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Abstract translation: 提供了包括n个堆叠芯片的堆叠半导体器件。 每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。 上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。 通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

公开(公告)号：US20110193086A1

公开(公告)日：2011-08-11

申请号：US12891141

申请日：2010-09-27

Applicant: Ho-Cheol LEE ,  Chi-Sung OH ,  Jin-Kuk KIM

Inventor： Ho-Cheol LEE ,  Chi-Sung OH ,  Jin-Kuk KIM

IPC: H01L27/118

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/06 ,  H01L22/32 ,  H01L24/09 ,  H01L24/73 ,  H01L27/0255 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/0912 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract translation: 半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。 半导体管芯包括多个存储单元阵列。 输入输出凸块焊盘部分形成在半导体管芯的中心区域。 输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。 半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

公开(公告)号：US20110093235A1

公开(公告)日：2011-04-21

申请号：US12900547

申请日：2010-10-08

Applicant: CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

Inventor： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

IPC: G01R31/14 ,  H03L7/00

CPC classification number: G01R31/2884 ,  G01R31/31726

Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Abstract translation: 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

公开(公告)号：US20110090754A1

公开(公告)日：2011-04-21

申请号：US12900624

申请日：2010-10-08

Applicant: Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

Inventor： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

IPC: G11C5/14 ,  G05F1/10

CPC classification number: G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

Abstract translation: 公开了一种用于半导体器件的内部发电系统。 该设备可以包括多个信道。 该系统包括被配置为产生参考电压的参考电压发生器。 该系统还包括多个内部功率发生器，其以一一对应的方式分配给多个通道，并且被配置为共同使用由参考电压发生器产生的参考电压。 每个内部发电机可以被配置为接收反馈内部电力电压，以将反馈内部电力电压与参考电压进行比较，并且基于该比较来产生内部电力电压。 该系统还包括多个通道状态检测器，其以一一对应的方式分配给多个通道，并且被配置为分别基于各个命令信号分别检测多个通道的操作状态 渠道。 该系统附加包括一对一对应地分配给多个通道的多个内部功率控制器，并且被配置为分别根据检测到的操作状态来控制内部电源电压的驱动能力。

公开(公告)号：US07870326B2

公开(公告)日：2011-01-11

申请号：US11819601

申请日：2007-06-28

Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

IPC: G06F12/00

CPC classification number: G06F12/02

Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

Abstract translation: 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。

公开(公告)号：US20080205175A1

公开(公告)日：2008-08-28

申请号：US12068280

申请日：2008-02-05

Applicant: Sang-Kyun Park ,  Ho-Cheol Lee

Inventor： Sang-Kyun Park ,  Ho-Cheol Lee

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

Abstract: An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.

Abstract translation: 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。 自动预充电控制电路可以包括用于接收包括时钟频率信息和等待时间信息中的至少一个的写入信号，时钟信号和至少一个控制信号的控制电路，并且输出至少一个路径信号; 自动预充电脉冲信号驱动器，用于接收至少一个路径信号，写入信号和使能信号，并产生自动预充电脉冲信号，所述自动预充电脉冲信号标识自动预充电操作的起始点; 以及自动预充电模式使能电路，用于接收时钟信号，自动预充电命令，有效信号和自动预充电脉冲信号，并产生使能信号。

公开(公告)号：US20080077937A1

公开(公告)日：2008-03-27

申请号：US11829859

申请日：2007-07-27

Applicant: Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

Inventor： Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

IPC: G06F15/167 ,  G06F9/30

CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

公开(公告)号：US20070150668A1

公开(公告)日：2007-06-28

申请号：US11548603

申请日：2006-10-11

Applicant: Kyoung-Hwan KWON ,  Dong-Il SEO ,  Ho-Cheol LEE ,  Han-Gu SOHN ,  Yun-Hee SHIN

Inventor： Kyoung-Hwan KWON ,  Dong-Il SEO ,  Ho-Cheol LEE ,  Han-Gu SOHN ,  Yun-Hee SHIN

IPC: G06F12/00

CPC classification number: G11C7/1075 ,  G06F13/1663 ,  G11C8/10 ,  G11C11/413

Abstract: A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

Abstract translation: 半导体存储器件包括端口，数据线对，其中与数据线对之一相关联的每个端口，地址线集合，其中每个端口与地址线中的一组相关联，存储器单元阵列的共享存储器区域 ，其中所述共享存储器区域可通过所述端口访问，访问控制器耦合到所述端口并且被配置为响应于通过所述端口接收的多个控制信号而生成访问选择信号;以及访问路由器，其耦合到所述共享存储器区域， 所述数据线对和所述地址线组，所述接入路由器被配置为响应于所述接入选择信号而选择性地将所述地址线组中的一个和所述数据线对之一耦合到所述共享存储器区域。