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    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line
    1.
    发明授权
    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
    具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法

    公开(公告)号：US08929118B2

    公开(公告)日：2015-01-06

    申请号：US13080061

    申请日：2011-04-05

    Applicant: Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    Inventor： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC: G11C5/06 ,  G11C5/02 ,  G11C7/10

    CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C7/1048

    Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    Abstract translation: 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08396682B2

    公开(公告)日：2013-03-12

    申请号：US12900547

    申请日：2010-10-08

    Applicant: Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    Inventor： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC: G01R27/28 ,  G06F19/00

    CPC classification number: G01R31/2884 ,  G01R31/31726

    Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    Abstract translation: 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory
    6.
    发明授权
    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory 有权
    内部发电装置，包括该内部发电装置的多通道存储器，以及采用多通道存储器的处理系统

    公开(公告)号：US08315121B2

    公开(公告)日：2012-11-20

    申请号：US12900624

    申请日：2010-10-08

    Applicant: Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    Inventor： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    IPC: G11C5/14

    CPC classification number: G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    Abstract: An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

    Abstract translation: 公开了一种用于半导体器件的内部发电系统。 该设备可以包括多个信道。 该系统包括被配置为产生参考电压的参考电压发生器。 该系统还包括多个内部功率发生器，其以一一对应的方式分配给多个通道，并且被配置为共同使用由参考电压发生器产生的参考电压。 每个内部发电机可以被配置为接收反馈内部电力电压，以将反馈内部电力电压与参考电压进行比较，并且基于该比较来产生内部电力电压。 该系统还包括多个通道状态检测器，其以一一对应的方式分配给多个通道，并且被配置为分别基于各个命令信号分别检测多个通道的操作状态 渠道。 该系统附加包括一对一对应地分配给多个通道的多个内部功率控制器，并且被配置为分别根据检测到的操作状态来控制内部电源电压的驱动能力。

    Multiprocessor system and method thereof
    8.
    发明申请
    Multiprocessor system and method thereof 审中-公开

    公开(公告)号：US20110107006A1

    公开(公告)日：2011-05-05

    申请号：US12929222

    申请日：2011-01-10

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC: G06F12/00

    CPC classification number: G06F12/02

    Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

    CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT
    9.
    发明申请
    CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT 有权
    用于产生内部电压的电路和方法，以及具有电路的半导体器件

    公开(公告)号：US20110095814A1

    公开(公告)日：2011-04-28

    申请号：US12845279

    申请日：2010-07-28

    Applicant: So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

    Inventor： So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

    IPC: G05F1/10

    CPC classification number: G11C5/14

    Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

    Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。

    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY
    10.
    发明申请
    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号：US20100309742A1

    公开(公告)日：2010-12-09

    申请号：US12768060

    申请日：2010-04-27

    Applicant: Ho-Cheol LEE ,  Jung-Bae LEE

    Inventor： Ho-Cheol LEE ,  Jung-Bae LEE

    IPC: G11C5/14 ,  G11C8/16

    CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

    Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

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