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    OPTICAL EQUALIZER FOR PHOTONICS SYSTEM
    41.
    发明申请
    OPTICAL EQUALIZER FOR PHOTONICS SYSTEM 审中-公开

    公开(公告)号：US20190212496A1

    公开(公告)日：2019-07-11

    申请号：US16352636

    申请日：2019-03-13

    Applicant: INPHI CORPORATION

    Inventor： Samira KARIMELAHI ,  Masaki KATO

    IPC: G02B6/293 ,  H04L25/03 ,  H04B10/25 ,  G02B6/28

    CPC classification number: G02B6/29391 ,  G02B6/2856 ,  G02B6/29344 ,  G02B6/29352 ,  H04B10/25 ,  H04L25/03885

    Abstract: The present disclosure provides an optical equalizer for photonics system in an electric-optical communication network. The optical equalizer includes an input port and an output port. Additionally, the optical equalizer includes a filter having a number of stages coupled to each other in a multi-stage series with an output terminal of any stage being coupled to an input terminal of an adjacent next stage while the input terminal of a first stage of the multi-stage series being coupled from the input port. Each stage includes a tap terminal configured to pass an optical power factored by a coefficient of multiplication from the corresponding input terminal of the stage to a tap-output path characterized by a corresponding phase delay. Furthermore, the optical equalizer includes a combiner configured to sum up the optical powers respectively from the number of tap-output paths of the multi-stage series to the output port.

    Soft FEC with parity check
    45.
    发明授权
    Soft FEC with parity check 有权

    公开(公告)号：US10326550B1

    公开(公告)日：2019-06-18

    申请号：US15691023

    申请日：2017-08-30

    Applicant: INPHI CORPORATION

    Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Sudeep Bhoja

    IPC: H04L1/00 ,  H03M13/29 ,  H03M13/15

    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

    FORWARD ERROR CORRECTION (FEC) EMULATOR
    46.
    发明申请
    FORWARD ERROR CORRECTION (FEC) EMULATOR 审中-公开

    公开(公告)号：US20190165806A1

    公开(公告)日：2019-05-30

    申请号：US16262148

    申请日：2019-01-30

    Applicant: INPHI CORPORATION

    Inventor： Andre SZCZEPANEK ,  Arash FARHOODFAR ,  Sudeep BHOJA ,  Sean BATTY ,  Shaun LYTOLLIS

    IPC: H03M13/01 ,  H03M13/15

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

    Channel diagnostics based on equalizer coefficients
    47.
    发明授权
    Channel diagnostics based on equalizer coefficients 有权

    公开(公告)号：US10305589B2

    公开(公告)日：2019-05-28

    申请号：US15838079

    申请日：2017-12-11

    Applicant: INPHI CORPORATION

    Inventor： Shih Cheng Wang ,  Seyedmohammadreza Motaghiannezam ,  Matthew C. Bashaw

    IPC: H04L5/00 ,  H04B10/079 ,  H04L27/01 ,  H04L25/03 ,  H04B10/07 ,  H04B10/2507 ,  H04B10/61 ,  H04L7/00

    Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

    Integrated photo detector, method of making the same
    49.
    发明授权
    Integrated photo detector, method of making the same 有权

    公开(公告)号：US10262983B2

    公开(公告)日：2019-04-16

    申请号：US15979046

    申请日：2018-05-14

    Applicant: INPHI CORPORATION

    Inventor： Jie Lin ,  Masaki Kato

    IPC: G02B6/12 ,  H01L27/02 ,  G02B6/42 ,  H01L31/02 ,  H01L31/0224 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/103 ,  H01L31/18

    Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

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