公开(公告)号：US20130075720A1

公开(公告)日：2013-03-28

申请号：US13554393

申请日：2012-07-20

Applicant: Byung Du AHN ,  Je Hun LEE ,  Sei-Yong PARK ,  Jun Hyun PARK ,  Gun Hee KIM ,  Ji Hun LIM ,  Jae Woo PARK ,  Jin Seong PARK ,  Toshihiro KUGIMIYA ,  Aya MIKI ,  Shinya MORITA ,  Tomoya KISHI ,  Hiroaki TAO

Inventor： Byung Du AHN ,  Je Hun LEE ,  Sei-Yong PARK ,  Jun Hyun PARK ,  Gun Hee KIM ,  Ji Hun LIM ,  Jae Woo PARK ,  Jin Seong PARK ,  Toshihiro KUGIMIYA ,  Aya MIKI ,  Shinya MORITA ,  Tomoya KISHI ,  Hiroaki TAO

IPC: H01L29/786 ,  H01L29/38

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/66969

Abstract: An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3.

Abstract translation: 氧化物半导体包括包含选自锌（Zn）和锡（Sn）中的至少一种的第一材料和第二材料，其中通过减去第二材料和氧之间的电负性差值获得的值（O ）从第一材料和氧（O）之间的电负性差值小于约1.3。

公开(公告)号：US20130032798A1

公开(公告)日：2013-02-07

申请号：US13642314

申请日：2011-04-18

Applicant: Aya Miki ,  Yumi Iwanari ,  Toshihiro Kugimiya ,  Shinya Morita ,  Yasuaki Terao ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn

Inventor： Aya Miki ,  Yumi Iwanari ,  Toshihiro Kugimiya ,  Shinya Morita ,  Yasuaki Terao ,  Satoshi Yasuno ,  Jae Woo Park ,  Je Hun Lee ,  Byung Du Ahn

IPC: C01G19/02 ,  C23C14/08 ,  C01G35/00 ,  H01L29/786 ,  C01F7/02

CPC classification number: H01L29/7869 ,  H01L21/02422 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78693

Abstract: Disclosed is an oxide for a semiconductor layer of a thin-film transistor, said oxide being excellent in the switching characteristics of a thin-film transistor, specifically enabling favorable characteristics to be stably obtained even in a region of which the ZnO concentration is high and even after forming a passivation layer and after applying stress. The oxide is used in a semiconductor layer of a thin-film transistor, and the aforementioned oxide contains Zn and Sn, and further contains at least one element selected from group X consisting of Al, Hf, Ta, Ti, Nb, Mg, Ga, and the rare-earth elements.

Abstract translation: 公开了一种用于薄膜晶体管的半导体层的氧化物，所述氧化物具有优异的薄膜晶体管的开关特性，特别是即使在ZnO浓度高的区域也能够稳定地获得良好的特性， 甚至在形成钝化层之后和施加应力之后。 氧化物用于薄膜晶体管的半导体层，上述氧化物含有Zn和Sn，还含有选自由Al，Hf，Ta，Ti，Nb，Mg，Ga组成的组X中的至少一种元素 ，和稀土元素。

公开(公告)号：US20120315731A1

公开(公告)日：2012-12-13

申请号：US13523767

申请日：2012-06-14

Applicant: Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

Inventor： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

IPC: H01L21/336

CPC classification number: G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

Abstract: A thin film transistor array panel is provided, which includes a plurality of gate line, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

Abstract translation: 提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个 包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

公开(公告)号：US20120211753A1

公开(公告)日：2012-08-23

申请号：US13328658

申请日：2011-12-16

Applicant: Ki-Won KIM ,  Je-Hun LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Seung-Ha CHOI

Inventor： Ki-Won KIM ,  Je-Hun LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Seung-Ha CHOI

IPC: H01L29/786 ,  H01L21/336 ,  H01L33/00

CPC classification number: H01L27/1225 ,  H01L27/1288

Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.

Abstract translation: 在显示基板和显示基板的制造方法中，显示基板包括数据线，通道图案，绝缘图案和像素电极。 数据线沿着基底基板上的方向延伸。 通道图案设置在与数据线连接的输入电极和与输入电极间隔开的输出电极之间的分离区域中。 通道图案与输入电极和输出电极上的输出电极接触。 绝缘图案与基底基板上的沟道图案间隔开，并且包括暴露输出电极的接触孔。 像素电极形成在绝缘图案上，以通过接触孔与输出电极接触。 因此，可以使氧化物半导体层的损伤最小化，并且可以简化制造工艺。

公开(公告)号：US08158499B2

公开(公告)日：2012-04-17

申请号：US12942910

申请日：2010-11-09

Applicant: Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

Inventor： Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

IPC: H01L21/20

CPC classification number: H01L27/124 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53238 ,  H01L27/12 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49117 ,  H01L2924/00

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy

Abstract translation: 提供一种线结构，制造线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。 导线结构包括形成在基板上的阻挡层，其包含形成在阻挡层上的包含铜或铜合金的二氧化铜和铜导电层

公开(公告)号：US20110284836A1

公开(公告)日：2011-11-24

申请号：US13080413

申请日：2011-04-05

Applicant: Je-Hun LEE ,  Jae-Woo PARK ,  Byung-Du AHN ,  Sei-Yong PARK ,  Jun-Hyun PARK

Inventor： Je-Hun LEE ,  Jae-Woo PARK ,  Byung-Du AHN ,  Sei-Yong PARK ,  Jun-Hyun PARK

IPC: H01L29/786

CPC classification number: H01L29/45 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a gate insulation layer and an oxide semiconductor pattern. The source and drain electrodes include a first metal element with a first oxide formation free energy. The oxide semiconductor pattern has a first surface making contact with the gate insulation layer and a second surface making contact with the source and drain electrodes to be positioned at an opposite side of the first surface. The oxide semiconductor pattern includes an added element having a second oxide formation free energy having an absolute value greater than or equal to an absolute value of the first oxide formation free energy, wherein an amount of the added element included in a portion near the first surface is zero or smaller than an amount of the added element included in a portion near the second surface.

Abstract translation: 薄膜晶体管包括栅电极，源电极，漏电极，栅极绝缘层和氧化物半导体图案。 源极和漏极包括具有第一氧化物形成自由能的第一金属元件。 氧化物半导体图案具有与栅极绝缘层接触的第一表面和与源极和漏极电极接触以与第一表面相对的第二表面。 氧化物半导体图案包括具有绝对值大于或等于第一氧化物形成自由能的绝对值的第二氧化物形成自由能的添加元素，其中包括在第一表面附近的部分中的添加元素的量 为零或小于包含在靠近第二表面的部分中的添加元素的量。

公开(公告)号：US20110149820A1

公开(公告)日：2011-06-23

申请号：US12970630

申请日：2010-12-16

Applicant: Je-Hun Lee ,  Sok-Kyu Lee

Inventor： Je-Hun Lee ,  Sok-Kyu Lee

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/23

Abstract: A method for adaptively performing power saving in a station of a wireless communication system includes: receiving first power-save capability information from an AP, the first power-save capability information containing information on power-save schemes supported by a MAC layer of the AP; transmitting second power-save capability information to the AP in response to the first power-save capability information, the second power-save capability information containing information on power-save schemes supported by a MAC layer of the station; transmitting power-save policy information, into which properties of traffics used in the station are reflected, to the AP; and performing a power-save function while interworking with the MAC layer of the station, according to the power-save policy information based on a predetermined power-save scheme.

Abstract translation: 一种用于在无线通信系统的站中自适应地执行省电的方法包括：从AP接收第一省电能力信息，所述第一节电能力信息包含由所述AP的MAC层支持的关于节能方案的信息 ; 响应于所述第一节电能力信息向所述AP发送第二节电能力信息，所述第二节电能力信息包含由所述站的MAC层支持的关于节能方案的信息; 向AP提供将车站使用的业务属性反映的节电政策信息; 并且根据基于预定的省电方案的省电策略信息，在与站的MAC层互通的同时执行省电功能。

公开(公告)号：US20110140103A1

公开(公告)日：2011-06-16

申请号：US13030213

申请日：2011-02-18

Applicant: Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

Inventor： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract translation: 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

公开(公告)号：US07928441B2

公开(公告)日：2011-04-19

申请号：US12417151

申请日：2009-04-02

Applicant: Je-hun Lee ,  Chang-ob Jeong ,  Jin-kwan Kim ,  Yang-bo Bae ,  Beom-seok Cho ,  Jun-hyung Souk

Inventor： Je-hun Lee ,  Chang-ob Jeong ,  Jin-kwan Kim ,  Yang-bo Bae ,  Beom-seok Cho ,  Jun-hyung Souk

IPC: H01L29/04

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/3276 ,  H01L29/4908 ,  H01L51/0021

Abstract: Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the aluminum layer may have a width about equal to a bottom surface of the molybdenum layer.Accordingly, it is an aspect of the present invention to provide a TFT array panel comprising an aluminum wiring on which aluminum protrusion is reduced or eliminated.

Abstract translation: 公开了诸如包括铝层的TFT阵列面板和形成在铝层上的钼层的显示部分。 钼层的厚度可以为铝层的厚度的约10％至约40％。 结果，铝层的顶表面可以具有大约等于钼层的底表面的宽度。 因此，本发明的一个方面是提供一种TFT阵列面板，其包括在其上减少或消除铝突起的铝布线。

公开(公告)号：US07915650B2

公开(公告)日：2011-03-29

申请号：US11930502

申请日：2007-10-31

Applicant: Je Hun Lee ,  Do Hyun Kim ,  Eun Guk Lee ,  Chang Oh Jeong

Inventor： Je Hun Lee ,  Do Hyun Kim ,  Eun Guk Lee ,  Chang Oh Jeong

IPC: H01L29/80 ,  H01L31/112

CPC classification number: H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract translation: 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。