公开(公告)号：US08426294B2

公开(公告)日：2013-04-23

申请号：US13476964

申请日：2012-05-21

Applicant: Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

Inventor： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

IPC: H01L29/76

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US08350316B2

公开(公告)日：2013-01-08

申请号：US12471287

申请日：2009-05-22

Applicant: Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

Inventor： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

IPC: H01L29/732

CPC classification number: H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

Abstract translation: 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

公开(公告)号：US20120327708A1

公开(公告)日：2012-12-27

申请号：US13472395

申请日：2012-05-15

Applicant: Pei-Ying DU ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

Inventor： Pei-Ying DU ,  Chao-I Wu ,  Ming-Hsiu Lee ,  Sangbum Kim ,  Chung Hon Lam

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0021

Abstract: Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.

Abstract translation: 基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。 响应于相变存储单元的置位或复位故障执行高电流修复操作。 更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。 通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。 这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。

公开(公告)号：US20120170359A1

公开(公告)日：2012-07-05

申请号：US12985253

申请日：2011-01-05

Applicant: Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

Inventor： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  H01L21/02

CPC classification number: H01L45/06 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C14/00 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.

Abstract translation: 一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。 预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。 设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

公开(公告)号：US08084761B2

公开(公告)日：2011-12-27

申请号：US11881077

申请日：2007-07-24

Applicant: Ming Hsiu Lee ,  Yi Chou Chen

Inventor： Ming Hsiu Lee ,  Yi Chou Chen

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2472 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/16

Abstract: A phase change device includes a first contact electrode structure a phase change material and a first insulating material between the phase change material and the first contact electrode structure and a second contact electrode in contact with the phase change material. A contact structure formed in the first insulating material between the first contact electrode structure and the phase change material is also included. The contact structure is formed by an insulating material breakdown process. A method of forming a phase change device is also described.

Abstract translation: 相变装置包括第一接触电极结构，相变材料和相变材料与第一接触电极结构之间的第一绝缘材料和与相变材料接触的第二接触电极。 还包括在第一接触电极结构和相变材料之间形成在第一绝缘材料中的接触结构。 接触结构由绝缘材料击穿过程形成。 还描述了形成相变装置的方法。

公开(公告)号：US08036014B2

公开(公告)日：2011-10-11

申请号：US12266222

申请日：2008-11-06

Applicant: Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam

Inventor： Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文所述的方法包括在增加脉冲高度的存储单元上施加固定的电压脉冲序列，以将电阻状态从较低电阻状态改变到较高电阻状态。 固定的电压脉冲序列导致增加的电流通过相变存储元件直到发生更高电阻状态的改变，并且在改变之后，固定序列中的电压脉冲导致相变存储元件上的电压小于阈值电压。

公开(公告)号：US20110121411A1

公开(公告)日：2011-05-26

申请号：US13022588

申请日：2011-02-07

Applicant: Ming-Hsiu Lee ,  Yen-Hao Shih

Inventor： Ming-Hsiu Lee ,  Yen-Hao Shih

IPC: H01L29/78

CPC classification number: G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention provides a semiconductor cell comprising a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.

Abstract translation: 本发明提供一种包括栅极，电介质层，沟道层，源极区，漏极区和氧化物区的半导体元件。 电介质层与栅极相邻。 沟道层与电介质层相邻并且形成在源极区，漏极区和氧化物区的上方。

公开(公告)号：US07897954B2

公开(公告)日：2011-03-01

申请号：US12249178

申请日：2008-10-10

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: H01L47/00 ,  H01L21/06

CPC classification number: G11C5/063 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C2213/34 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.

Abstract translation: 存储器件包括底部和顶部电极结构以及它们之间的存储单元。 存储单元包括底部和顶部存储器元件以及它们之间的介电元件。 通过介电元件形成较低的电阻传导路径。 电介质元件可以具有外边缘和中心部分，外边缘比中心部分厚。 为了制造存储器件，通过存储器单元施加电脉冲以形成穿过介质元件的传导路径。 可以通过氧化存储单元的外表面来形成钝化元件，该外表面也可以增大电介质元件的外边缘。

公开(公告)号：US20110012083A1

公开(公告)日：2011-01-20

申请号：US12534599

申请日：2009-08-03

Applicant: Ming-Hsiu Lee ,  Chieh-Fang Chen

Inventor： Ming-Hsiu Lee ,  Chieh-Fang Chen

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L45/1273 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract translation: 本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。 绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。 底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。 顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

公开(公告)号：US20100009504A1

公开(公告)日：2010-01-14

申请号：US12561395

申请日：2009-09-17

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract translation: 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。