公开(公告)号：US08391054B2

公开(公告)日：2013-03-05

申请号：US13235232

申请日：2011-09-16

Applicant: Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  B82Y10/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract translation: 多状态电流切换磁存储元件包括由用于存储多于一位的信息的非磁性层分开的磁隧道结（MTJ）堆叠，其中施加到存储元件的不同电流电平导致切换到不同的 状态。

公开(公告)号：US08291128B2

公开(公告)日：2012-10-16

申请号：US13311150

申请日：2011-12-05

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is configured to identify an operating mode of the host computer system from comparing applied signals to sensed signals.

Abstract translation: 具有主计算机系统的系统，耦合到主计算机系统的存储器件以及识别电路。 识别电路被配置为通过将应用的信号与感测的信号进行比较来识别主计算机系统的操作模式。

公开(公告)号：US20120079137A1

公开(公告)日：2012-03-29

申请号：US13311150

申请日：2011-12-05

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F3/00 ,  G06F12/02

CPC classification number: G11C7/1045 ,  G06F13/4081 ,  G11C7/20

Abstract: Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is configured to identify an operating mode of the host computer system from comparing applied signals to sensed signals.

Abstract translation: 具有主计算机系统的系统，耦合到主计算机系统的存储器件以及识别电路。 识别电路被配置为通过将应用的信号与感测的信号进行比较来识别主计算机系统的操作模式。

公开(公告)号：US20120068236A1

公开(公告)日：2012-03-22

申请号：US13305668

申请日：2011-11-28

Applicant: Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Petro Estakhri ,  Mahmud Assar ,  Parviz Keshtbod

IPC: H01L29/82 ,  H01L43/12

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

公开(公告)号：US08120949B2

公开(公告)日：2012-02-21

申请号：US12182996

申请日：2008-07-30

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

IPC: G11C11/14

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die.

Abstract translation: 闪存RAM存储器包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器， 易失性RAM驻留在单片模具上。

公开(公告)号：US07774576B2

公开(公告)日：2010-08-10

申请号：US12426662

申请日：2009-04-20

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F12/08 ,  G06F9/24 ,  G06F9/34

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US07523249B1

公开(公告)日：2009-04-21

申请号：US11165864

申请日：2005-06-24

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F12/10

CPC classification number: G11C29/765 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/023 ,  G06F12/0246 ,  G11C16/08 ,  G11C16/102 ,  G11C29/82

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract translation: 非易失性半导体大容量存储系统和架构可以代替旋转硬盘。 每当存储在大容量存储器中的信息改变时，系统和架构避免了擦除周期。 通过将更改的数据文件编程为空的大容量存储块而不是以硬盘为单位，可以避免擦除周期。 定期地，大容量存储将需要清理。 这些优点通过使用多个标志来实现，以及将块的逻辑块地址与该块的物理地址相关联的映射。 特别地，为缺陷块，使用的块和块的旧版本提供标志。 易失性存储器阵列根据逻辑地址可寻址，并存储物理地址。

公开(公告)号：US06721819B2

公开(公告)日：2004-04-13

申请号：US09940972

申请日：2001-08-28

Applicant: Petro Estakhri ,  Mahmud Assar

Inventor： Petro Estakhri ,  Mahmud Assar

IPC: G06F1300

CPC classification number: G11C7/20 ,  G06F13/387 ,  G06F13/4081 ,  G06F2213/0042 ,  G11C7/1045

Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols. Upon initialization with the interface device, the flash memory card automatically detects the selected operating mode of the interface device and configures itself to operate with the selected operating mode. The operating mode detection is accomplished by sensing unencoded signals and encoded signals. The encoded signals are encoded with a finite set of predetermined codes. Each predetermined code uniquely identifies a particular operating mode.

Abstract translation: 一种接口系统，在主计算机系统和闪存卡之间以选定的操作模式促进用户友好的连接。 接口系统包括接口设备和闪存卡。 接口系统具有显着扩展闪存卡内的工作模式检测功能，并显着减少了操作模式的错误检测。 接口设备包括用于耦合到主计算机的第一端和用于耦合到闪存卡的第二端，同时支持主机计算机系统也支持的所选操作模式中的通信。 闪存卡利用五十针连接通过接口设备与主机系统进行接口。 闪存卡的五十针连接可以在各种配置中使用，例如通用串行模式，PCMCIA模式和ATA IDE模式。 这些操作模式中的每一种都需要不同的协议。 在使用接口设备进行初始化时，闪存卡会自动检测接口设备的选定操作模式，并配置自身以所选择的操作模式进行操作。 通过感测未编码的信号和编码信号来实现操作模式检测。 编码信号用有限的一组预定码进行编码。 每个预定代码唯一地标识特定的操作模式。

公开(公告)号：US06587382B1

公开(公告)日：2003-07-01

申请号：US10175928

申请日：2002-06-19

Applicant: Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

Inventor： Petro Estakhri ,  Siamack Nemazie ,  Mahmud Assar ,  Parviz Keshtbod

IPC: G11C1604

CPC classification number: G11C16/102 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C8/12 ,  G11C16/08

Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

公开(公告)号：US5926055A

公开(公告)日：1999-07-20

申请号：US771619

申请日：1996-12-20

Applicant: Abdual Q. Kashmiri ,  Mahmud Assar

Inventor： Abdual Q. Kashmiri ,  Mahmud Assar

IPC: H02J1/00 ,  G05F3/24 ,  H03K19/003 ,  H03K19/0185 ,  H03L5/00

CPC classification number: H03K19/018521 ,  H03K19/00315

Abstract: An output circuit for producing 5 volt output signals from a chip that is manufactured in a 3 volt process, is provided with a control signal logic circuit, a pseudoground generating circuit, and an output signal generation circuit. The control signal logic circuit receives 3 volt data signals from the internal logic circuitry of the chip, and produces control signals as a function of these 3 volt data signals. The pseudoground generating circuit is coupled to the control signal logic circuit and generates a pseudoground greater than zero volts and intermediate output signals as a function of the control signals produced by the control signal logic circuit. The output signal generation circuit is coupled to the pseudoground generating circuit and generates the 5 volt output signals as a function of the intermediate output signals generated by the pseudoground generating circuit. As a result of the creation of the pseudoground, the voltage differential to which the semiconductor devices in the output circuit are subjected is always less than 5 volts. This prevents the rapid degradation of the oxide layer in the semiconductor devices of the output circuit, allowing the 3 volt process chip to interface with 5 volt process devices without premature failure of the chip.

Abstract translation: 用于以3伏工艺制造的芯片产生5伏输出信号的输出电路设置有控制信号逻辑电路，伪距发生电路和输出信号发生电路。 控制信号逻辑电路从芯片的内部逻辑电路接收3伏数据信号，并产生作为这3V数据信号的函数的控制信号。 伪距发生电路耦合到控制信号逻辑电路，并产生大于零伏特的伪距和作为由控制信号逻辑电路产生的控制信号的函数的中间输出信号。 输出信号发生电路耦合到伪距发生电路，并产生5伏输出信号作为由伪距产生电路产生的中间输出信号的函数。 作为伪环的创建的结果，输出电路中的半导体器件所经受的电压差总是小于5伏特。 这防止输出电路的半导体器件中的氧化物层的快速劣化，从而允许3伏工艺芯片与5伏工艺器件接合而不会使芯片发生过早的故障。