公开(公告)号：US5157480A

公开(公告)日：1992-10-20

申请号：US651166

申请日：1991-02-06

Applicant: Michael B. McShane ,  Paul T. Lin

Inventor： Michael B. McShane ,  Paul T. Lin

IPC: H01L23/495 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L23/49555 ,  H01L23/49517 ,  H01L23/49551 ,  H05K3/341 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/0206 ,  H05K2201/09054 ,  H05K2201/09954 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613

Abstract: A semiconductor device having both bottom-side contacts and peripheral contacts provides surface mounting options. In one form, a semiconductor device die is positioned at a die receiving area of a leadframe. The leadframe also has a plurality of leads, each lead having a first and a second contact portion which are separated by an intermediate portion. A package body encapsulates the semiconductor device die and intermediate portions of the plurality of leads. The first contact portions of the leads are partially exposed on the bottom surface of the package body. The second contact portions extend from the package body along a portion of the package body perimeter. The first contact portions provide bottom-side contacts to the device, while the second contact portions provide peripheral contacts. The second contact portions are shaped into a desired lead configuration or are severed to establish a leadless device.

Abstract translation: 具有两个底侧触点和外围触点的半导体器件提供表面安装选项。 在一种形式中，半导体器件裸片位于引线框的管芯接收区域。 引线框架还具有多个引线，每个引线具有由中间部分分开的第一和第二接触部分。 封装体封装半导体器件裸片和多个引线的中间部分。 引线的第一接触部分部分地暴露在封装主体的底表面上。 第二接触部分沿着包装体周边的一部分从包装体延伸。 第一接触部分向器件提供底侧触点，而第二接触部分提供周边接触。 第二接触部分被成形为所需的引线结构或被切断以建立无引线器件。

公开(公告)号：US5053357A

公开(公告)日：1991-10-01

申请号：US567838

申请日：1990-08-14

Applicant: Paul T. Lin ,  Michael B. McShane

Inventor： Paul T. Lin ,  Michael B. McShane

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30

CPC classification number: H01L22/00 ,  H01L23/3121 ,  H01L23/4985 ,  H05K3/303 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K2201/10303 ,  H05K2201/10681 ,  H05K2203/162 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49121

Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternative version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB. A variety of outer bonding area pitches may be provided on the same package with test points of a standard pitch. The relatively inexpensive device is thin and easily mounted by conventional techniques.

Abstract translation: 具有其上具有导电迹线的柔性基板的电子部件可以将引线分离成阵列，其被成形为接触并被表面安装到印刷电路板（PCB）上的接合焊盘。 柔性基板，例如聚酰亚胺，粘附到迹线上并与它们形成引线阵列。 因此，在处理和安装到PCB期间，引线阵列使引线的部分和对应的引线阵列相对于彼此对准。 对准机构可以任选地存在于与PCB上的对应机构相配合的引线阵列上。 封装主体本身可以被包覆成型，从现有部件组装等。另一替代形式包括超出可用于测试该器件（例如集成电路芯片或裸片）的外部接合区域的衬底周边上的测试点， 在装配过程的中间阶段。 在封装安装到PCB之前，外围和测试点可以剪切掉。 可以在相同的包装上提供各种外部粘合区域间距，其具有标准节距的测试点。 相对便宜的装置是薄且易于通过常规技术安装的。

公开(公告)号：US4897602A

公开(公告)日：1990-01-30

申请号：US258235

申请日：1988-10-14

Applicant: Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz ,  Joan M. Hamilton

Inventor： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz ,  Joan M. Hamilton

IPC: H01L21/68 ,  H01L21/683

CPC classification number: H01L21/68 ,  H01L21/6835

Abstract: An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

Abstract translation: 引线框架上的电子器件封装，其具有将引线的远端固定在刚性位置的外围载体结构。 承载结构与包装主体间隔开并允许在保护引线的同时处理和测试包装。 对于载体结构而言，与包装体相比，使用不同的，相对较低的质量和较便宜的材料来降低包装的成本，因为载体结构可以包括包装体的体积的几倍，例如四倍或更多倍 。

公开(公告)号：US4791075A

公开(公告)日：1988-12-13

申请号：US104478

申请日：1987-10-05

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/057 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/057 ,  H01L23/49827 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49153 ,  Y10T29/49162

Abstract: A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Abstract translation: 一种制造密封，低成本针阵列（PGA）半导体管芯封装的工艺。 该方法涉及将半导体管芯或集成电路芯片裸片接合到其上具有互连或金属化图案的衬底。 模具电连接到图案，然后模具和内部结合件密封在小于衬底的帽内，使得金属化图案的端部露出。 然后将引线例如通过焊料或其它技术电连接到图案的暴露端。

公开(公告)号：US4661887A

公开(公告)日：1987-04-28

申请号：US793414

申请日：1985-10-31

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/50 ,  H05K1/18 ,  H05K3/34 ,  H05K13/04 ,  H01R9/09

CPC classification number: H05K3/3426 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/1084 ,  H05K2201/10984 ,  Y02P70/613 ,  Y10T29/49144

Abstract: An integrated circuit package having a plurality of leads capable of holding a quantity of solder paste prior to bonding to a printed circuit board or other substrate. The solder paste bearing structure may be straight or spiral grooves, or even a slot or roughened surface, running down at least the lower length of the leads as long as some mechanism is present which will first hold the solder paste or other electrically conductive binder on the lead and then deliver the binder to the end of the lead to produce an electrical and structural bond in a binder flowing operation. Application of the solder paste to the leads is accomplished by simply dipping the package leads into the paste thereby eliminating the need to make a solder mask for the substrate as well as the task of aligning the mask to the substrate.

Abstract translation: 一种集成电路封装，其具有多个引线，其能够在与印刷电路板或其它基板接合之前保持一定量的焊膏。 焊膏支承结构可以是直的或螺旋形的沟槽，或者甚至是槽或粗糙表面，只要存在一些将首先将焊膏或其它导电粘合剂保持在其上的机构，至少沿着引线的较低长度向下延伸 引线，然后将粘合剂输送到引线的末端，以在粘合剂流动操作中产生电和结构粘合。 通过将封装引线简单地浸入糊料中，可以将焊膏施加到引线上，从而不需要为衬底制造焊接掩模以及将掩模对准衬底的任务。

公开(公告)号：US4038488A

公开(公告)日：1977-07-26

申请号：US576298

申请日：1975-05-12

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K5/00

CPC classification number: H01L23/49822 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2924/0002

Abstract: A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas. Finger areas on one side of a chip receiving cavity are offset with respect to the finger areas on the opposite side of the same chip receiving cavity but aligned with the finger areas on an adjacent chip receiving cavity to minimize crossover connections as well as the electrical coupling. An identical bonding design for each cavity also results. A lead frame is brazed to the substrate at its edges. A lid is bonded to the top surface of the substrate to hermetically seal chips within the chip receiving cavities thereby completing assembly of the package.