公开(公告)号：US5450283A

公开(公告)日：1995-09-12

申请号：US179892

申请日：1994-01-10

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H05K7/20

CPC分类号： H01L21/568 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/18161

摘要： A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.

摘要翻译： 描述具有暴露背面（22）的热增强半导体器件（10）。 在一个实施例中，提供在基板的上表面和下表面上具有导电迹线（14）图案的PC板基板（12）。 在具有导电通孔（16）的两个表面之间保持电连续性。 半导体管芯（18）被翻转安装到衬底的上表面。 焊接凸块（26）将管芯电连接到导电迹线，底部填充物（28）将管芯的有效侧（20）连接到衬底的上表面。 围绕模具的周边（24）形成包装体（40），留下非活性背面，以增强散热。 不活动的背面还可以耦合到散热器以增加散热。 电连接到导电迹线的多个焊球（42）附接到基板的下表面。

公开(公告)号：US5006922A

公开(公告)日：1991-04-09

申请号：US480386

申请日：1990-02-14

申请人： Michael B. McShane ,  Paul T. Lin ,  Howard P. Wilson

发明人： Michael B. McShane ,  Paul T. Lin ,  Howard P. Wilson

IPC分类号： H01L23/04 ,  H01L23/057 ,  H01L23/498

CPC分类号： H01L23/49827 ,  H01L23/04 ,  H01L23/057 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041

摘要： An improved packaged semiconductor device is provided having an electronic component, such as an integrated circuit, enclosed within a single layer ceramic PGA package. A cap, of substantially the same areal dimension as the base, is sealed to the base forming a cavity in which the integrated circuit is mounted. Input/output pins are attached to through-holes in the base and extend through the base and are exposed by holes in the cap aligned to the through-holes in the base. Extensive glass sealing of the cap to the base, made possible by the substantially co-extensive nature of the cap with respect to the base, provides a sturdy highly reliable seal making the packaged semiconductor device better able to withstand mechanical stress.

摘要翻译： 提供了一种改进的封装半导体器件，其具有封装在单层陶瓷PGA封装内的诸如集成电路的电子部件。 与基座基本上相同的面积尺寸的盖子密封到形成其中安装集成电路的空腔的基座。 输入/输出引脚连接到基座中的通孔并延伸穿过基座，并且通过与基座中的通孔对准的盖中的孔露出。 通过盖相对于基座的基本上共同的性质，可以将盖子广泛地密封到基座上，从而提供坚固的高度可靠的密封，使得封装的半导体器件能够更好地承受机械应力。

公开(公告)号：US4837184A

公开(公告)日：1989-06-06

申请号：US141013

申请日：1988-01-04

申请人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz

发明人： Paul T. Lin ,  Michael B. McShane ,  Charles G. Bigler ,  John A. Goertz

IPC分类号： H01L23/28 ,  H01L21/68 ,  H01L21/683 ,  H01L23/50

CPC分类号： H01L21/6835 ,  H01L21/68 ,  H01L2224/48091 ,  H01L2224/48247 ,  Y10T29/49004 ,  Y10T29/49121 ,  Y10T29/49172

摘要： An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while protecting the leads. A different, relatively lower quality and less expensive material is used for the carrier structure than for the package body to reduce the cost of the package since the carrier structure may comprise several times, for example four times or more, the volume of the package body.

摘要翻译： 引线框架上的电子器件封装，其具有将引线的远端固定在刚性位置的外围载体结构。 承载结构与包装主体间隔开并允许在保护引线的同时处理和测试包装。 对于载体结构而言，与包装体相比，使用不同的，相对较低的质量和较便宜的材料来降低包装的成本，因为载体结构可以包括包装体的体积的几倍，例如四倍或更多倍 。

公开(公告)号：US5247423A

公开(公告)日：1993-09-21

申请号：US887963

申请日：1992-05-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14

CPC分类号： H01L23/4985 ,  H01L23/3121 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/144 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025

摘要： A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

公开(公告)号：US5049526A

公开(公告)日：1991-09-17

申请号：US362644

申请日：1989-06-07

申请人： Michael B. McShane ,  Paul T. Lin

发明人： Michael B. McShane ,  Paul T. Lin

IPC分类号： B29C45/14 ,  H01L21/56

CPC分类号： B29C45/14655 ,  H01L21/565 ,  H01L2224/48247 ,  Y10T29/49121

摘要： A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area. A semiconductor device die is secured to the lead frame and the lead frame with the die attached is aligned within the encapsulation mold to place the semiconductor device die and the inner ends of the leads within the cavity defined by the inserts. The outer ends of the leads extend through the second chamber. Plastic material is then injected into the mold to form the device package body about the semiconductor device die. The package body is shaped by the cavity and the inserts and the carrier ring is shaped by the second chamber.

公开(公告)号：US20120020040A1

公开(公告)日：2012-01-26

申请号：US13136185

申请日：2011-07-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H05K1/18

CPC分类号： H05K1/144 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.

摘要翻译： 本发明公开了一种用于制造包含并保护集成电路（IC）芯片的封装到封装（P2P）堆叠模块的电子封装的结构和工艺。 该方法包括提供插入件的步骤，该插入件包括在布置在顶部和/或底部表面上的预先指定的接触垫之间互连的导电迹线，用于安装IC芯片的至少顶部或底部封装，其中电气端子与设置的接触焊盘接触 在插入器的顶部和/或底部表面上。 支架和无源元件也可以添加到插入器上，以便同时提高焊点的可靠性，电气性能和主板密度。 将无源部件包含在插入器上可以增强成品封装堆叠的电性能和可测试性。

公开(公告)号：US5468999A

公开(公告)日：1995-11-21

申请号：US249602

申请日：1994-05-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L23/24 ,  H01L23/31 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107

摘要： A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

摘要翻译： 球栅阵列半导体器件（10）包括具有多个导电迹线（18），接合柱（20）和导电通孔（22）的封装衬底（14或16）。 半导体管芯（12）安装到封装衬底上。 正交线接合（28）用于将交错的接合焊盘（26）电连接到衬底上的对应的接合柱（20）。 液体密封剂（40）用于覆盖模具，引线键合和封装衬底的部分。 在另一个实施例中，封装衬底（50）包括下结合层（52）和上结合层（54）。 线接合（60）用于将外排的接合焊盘（64）电连接到下层（52）的接合柱（20），而引线接合（62）用于电连接内排接合焊盘 64）到上层（54）的粘合柱（20）。 引线键（60）的环路高度小于引线键合（62）。

公开(公告)号：US5273938A

公开(公告)日：1993-12-28

申请号：US876315

申请日：1992-04-30

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/498 ,  H05K3/34 ,  H01L21/28 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3431 ,  Y10T29/49146

摘要： A low cost manufacturing method is used to fabricate a small multichip semiconductor device (30). In one embodiment, a pattern of conductive traces (13) is formed on a film of transfer material (12). A first semiconductor die (15) is interconnected to the traces and a resin body (20) is formed around the first die and one side of the traces. The film of transfer material forms, at this stage of the process, one side of the first package. The film of transfer material is then peeled from the pattern of conductive traces and the first resin body to expose the other side of the traces. A second semiconductor die (23) is interconnected to the exposed side of the traces. A second resin body (25) is formed around the second die and portions of the exposed traces. Solder balls (26) are coupled to the exposed portions of the traces to establish external electrical connections to each die.

摘要翻译： 使用低成本制造方法来制造小型多芯片半导体器件（30）。 在一个实施例中，导电迹线（13）的图案形成在转印材料（12）的膜上。 第一半导体管芯（15）与迹线相互连接，树脂体（20）围绕第一管芯和迹线的一侧形成。 在该过程的这个阶段，转印材料的薄膜形成第一包装的一面。 然后将转印材料的膜从导电迹线图案和第一树脂体的图案剥离，以露出迹线的另一侧。 第二半导体管芯（23）与迹线的暴露侧相互连接。 第二树脂体（25）围绕第二管芯和暴露的迹线的一部分形成。 焊球（26）耦合到迹线的暴露部分以建立到每个管芯的外部电连接。

公开(公告)号：US5216278A

公开(公告)日：1993-06-01

申请号：US841765

申请日：1992-03-02

申请人： Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

发明人： Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L23/49827 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

摘要翻译： 一种半导体器件（10），其具有通过形成在所述载体衬底（12）中的通孔（32）互连的载体衬底（12）的相对表面上的第一和第二布线层（30,33），所述通孔（32）将电子部件（18）电耦合到 通过从通孔（32）移开的柔性焊球（26）的安装基板，所述半导体器件（10）的特征在于具有高性能电气封装互连（24）和良好散热的标准尺寸的载体衬底（12）。 通过提供独立的布线层（30,33）来获得改善的电性能，每个独立布线层具有专门为特定的电子部件（18）设计的引线迹线布局和特定的板连接要求，同时使用标准尺寸封装轮廓。 通过在能够支撑本身具有不同尺寸的各种不同的电子部件（18）的标准尺寸的载体基板（12）上提供塑料封装模具（36）来减少装配成本。

公开(公告)号：US5045914A

公开(公告)日：1991-09-03

申请号：US663225

申请日：1991-03-01

申请人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

发明人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/10 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49517 ,  H01L23/49589 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/09709 ,  H05K2201/10515 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K3/3426 ,  Y02P70/613

摘要： A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting. The open vias permit back side testing of the device before or after mounting of the package to the PCB. Additionally, a heat sink structure and/or capacitor may be directly bonded to the side or the top of the pad array electronic device which may be used singly or in multiple, stacked configurations, to facilitate the thermal dissipation from the device.

摘要翻译： 用于安装在诸如印刷电路板（PCB）的基板上的焊盘阵列电子器件具有相对刚性的封装体，其具有多个孔，该多个孔承载用于结合到PCB上的焊盘的连接机构。 封装体可以是可以围绕电子部件注射模制的热固性塑料或其它材料，例如结合到引线框架的集成电路（IC）。 集成电路芯片或其他电子部件安装在引线框架附近或之上，并且通过任何常规方式制造集成电路芯片和框架之间的电连接。 在一个方面，衬底引线设置在其外端处，其被封装中的孔暴露以用于与PCB连接的焊球或焊盘。 封装体可以可选地用于从PCB离开设备一定距离，使得焊球将形成适当的凹形结构。 封装主体的周边可以用作载体结构，以在测试，处理和板安装期间保护引线或连接结构。 打开的通孔允许在将封装安装到PCB之前或之后对器件进行背面测试。 此外，散热器结构和/或电容器可以直接结合到可以单独使用或以多个堆叠配置使用的焊盘阵列电子器件的侧面或顶部，以便于从器件散热。