公开(公告)号：US06965253B1

公开(公告)日：2005-11-15

申请号：US10710298

申请日：2004-06-30

Applicant: Wensong Chen ,  Paul C. F. Tong ,  Ping Ping Xu ,  Zhi Qing Liu

Inventor： Wensong Chen ,  Paul C. F. Tong ,  Ping Ping Xu ,  Zhi Qing Liu

IPC: H03K17/16 ,  H03K19/0175

CPC classification number: H03K17/162

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract translation: 总线开关具有降低的输入电容。 寄生源阱和漏 - 阱电容器由短路晶体管短路，消除了这些寄生电容。 当总线开关晶体管导通时，短路晶体管导通，而当总线开关晶体管关断时总线开关晶体管导通，并且总线开关将源极和漏极上的信号隔离。 总线开关晶体管和短路晶体管之间的隔离P阱不接地。 相反，当总线开关晶体管导通时，隔离的P阱是浮置的。 当总线开关晶体管截止时，下一个隔离P阱通过另一个P阱中的偏置晶体管被驱动到地。 由于隔离的P阱具有比N +源极和漏极低得多的掺杂，所以阱到衬底结的电容远小于源极 - 阱电容。 因此，输入电容减小，允许更高频率的切换。

公开(公告)号：US06890850B2

公开(公告)日：2005-05-10

申请号：US10196498

申请日：2002-07-15

Applicant: Ju-Hyung Lee ,  Ping Xu ,  Shankar Venkataraman ,  Li-Qun Xia ,  Fei Han ,  Ellie Yieh ,  Srinivas D. Nemani ,  Kangsub Yim ,  Farhad K. Moghadam ,  Ashok K. Sinha ,  Yi Zheng

Inventor： Ju-Hyung Lee ,  Ping Xu ,  Shankar Venkataraman ,  Li-Qun Xia ,  Fei Han ,  Ellie Yieh ,  Srinivas D. Nemani ,  Kangsub Yim ,  Farhad K. Moghadam ,  Ashok K. Sinha ,  Yi Zheng

IPC: C23C16/42 ,  C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829

Abstract: Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising an oxygen-containing organosilicon compound, carbon dioxide, or combinations thereof, and an oxygen-free organosilicon compound to the processing chamber, and reacting the processing gas to deposit an oxygen-doped dielectric material on the substrate, wherein the dielectric material has an oxygen content of about 15 atomic percent or less. The oxygen-doped dielectric material may be used as a barrier layer in damascene or dual damascene applications.

Abstract translation: 提供了用于沉积氧掺杂介电层的方法。 氧掺杂介电层可用于阻挡层或硬掩模。 在一个方面，提供了一种处理衬底的方法，包括将衬底定位在处理室中，将包含含氧有机硅化合物，二氧化碳或其组合的处理气体和无氧有机硅化合物引入到处理 并且使所述处理气体反应以在所述衬底上沉积掺杂氧的电介质材料，其中所述介电材料的氧含量为约15原子％或更低。 氧掺杂的电介质材料可以用作镶嵌或双镶嵌应用中的阻挡层。

公开(公告)号：US06868856B2

公开(公告)日：2005-03-22

申请号：US09905515

申请日：2001-07-13

Applicant: Thomas Nowak ,  Ian Latchford ,  Tsutomu Tanaka ,  Bok Heon Kim ,  Ping Xu ,  Jason Foster ,  Heath B. DeShong ,  Martin Seamons

Inventor： Thomas Nowak ,  Ian Latchford ,  Tsutomu Tanaka ,  Bok Heon Kim ,  Ping Xu ,  Jason Foster ,  Heath B. DeShong ,  Martin Seamons

IPC: B08B7/00 ,  C23C16/44 ,  C23C16/52 ,  H01J37/32 ,  B08B6/00 ,  H01L21/306

CPC classification number: H01J37/32862 ,  B08B7/00 ,  C23C16/4405 ,  C23C16/52 ,  Y10S134/902

Abstract: Methods and apparatus for cleaning semiconductor processing equipment. The apparatus include both local and remote gas dissociators coupled to a semiconductor processing chamber to be cleaned. The methods include introducing a precursor gas into the remote dissociator where the gas is dissociated and introducing a portion of the dissociated gas into the chamber. Another portion of the dissociated gas which re-associates before introduction into the chamber is also introduced into the chamber where it is again dissociated. The dissociated gas combines with contaminants in the chamber and is exhausted from the chamber along with the contaminants.

Abstract translation: 半导体加工设备清洗方法及装置。 该装置包括耦合到待清洁的半导体处理室的局部和远程气体离解器。 所述方法包括将前体气体引入到远离解离器中，其中气体被解离并将一部分解离的气体引入室中。 在引入室之前重新结合的解离气体的另一部分也被引入室中，在那里再次解离。 解离的气体与室内的污染物结合，并与污染物一起从室中排出。

公开(公告)号：US06849562B2

公开(公告)日：2005-02-01

申请号：US10092203

申请日：2002-03-04

Applicant: Chi-I Lang ,  Li-Qun Xia ,  Ping Xu ,  Louis Yang

Inventor： Chi-I Lang ,  Li-Qun Xia ,  Ping Xu ,  Louis Yang

IPC: C23C16/36 ,  H01L21/31 ,  H01L21/469

CPC classification number: C23C16/36

Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.

Abstract translation: 提供了沉积包含硅，碳和氮的低k电介质膜的方法。 低k电介质膜由包含硅源，碳源和NR1R2R3的气体混合物形成，其中R1，R2和R3选自烷基和苯基。 低k电介质膜可以用作阻挡层，蚀刻停止层，抗反射涂层或硬掩模。

公开(公告)号：US6066985A

公开(公告)日：2000-05-23

申请号：US152026

申请日：1998-09-10

Applicant: Ping Xu

Inventor： Ping Xu

IPC: H03M1/12 ,  H03F3/30 ,  H03F3/45 ,  H03K19/0175

CPC classification number: H03F3/3028 ,  H03F3/4521 ,  H03F2203/45508

Abstract: An analog buffer comprising a bias circuit, an n input stage, a p-input stage, and a push-pull output stage which generates an output voltage signal and which is configured and operated such that the output voltage signal is able to quickly and accurately respond to changes in the input voltage signal. The push-pull output stage comprises a pair of output transistors which having a common drain connection forming an output node where the output voltage signal is generated. The push-pull output stage further comprises a first group of PMOS transistors, one of which is responsive to a first control signal generated in the n-input stage to increase the output signal in response to an increase in the input signal, and a second group of NMOS transistors, one of which is responsive to a second control signal generated in the p-input stage to decrease the output signal in response to a decrease in the input signal. A third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input signal range, and a fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input signal range.

Abstract translation: 一种模拟缓冲器，包括偏置电路，n输入级，p输入级和推挽输出级，其产生输出电压信号，并被配置和操作，使得输出电压信号能够快速且准确地 响应输入电压信号的变化。 推挽输出级包括一对输出晶体管，其具有共同的漏极连接，形成输出电压信号的输出节点。 推挽输出级还包括第一组PMOS晶体管，其中一个PMOS晶体管响应于在n输入级中产生的第一控制信号响应输入信号的增加来增加输出信号，第二组PMOS晶体管 一组NMOS晶体管，其中之一响应于在p输入级中产生的第二控制信号，以响应于输入信号的减小而减小输出信号。 第三组MOS晶体管有助于响应于在输入信号范围的相对高端的输入信号的增加而增加输出信号，并且第四组MOS晶体管有助于响应于减小而减小输出信号 在输入信号的输入信号范围相对较低的一端。

公开(公告)号：US5705921A

公开(公告)日：1998-01-06

申请号：US635022

申请日：1996-04-19

Applicant: Ping Xu

Inventor： Ping Xu

IPC: G05F3/20 ,  G05F3/16 ,  H02J1/04

CPC classification number: G05F3/205

Abstract: The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.

Abstract translation: 本发明涉及一种用于实现低噪声偏置电路的电路，其在3伏特，5伏特或任何期望的电源电压下工作，同时避免生产重新配置或后期制作配置。 通过使用设计成在不同条件（例如，诸如温度变化，电源变化或快速晶体管工艺中遇到的条件）中提供恒定电流的电流源来实现本发明。 本电路提供了适应变化条件的手段。 本电路通常提供两个偏置信号，通常用于实现NMOS和PMOS晶体管的预驱动电路。

公开(公告)号：US09274274B1

公开(公告)日：2016-03-01

申请号：US14590284

申请日：2015-01-06

Applicant: Ping Xu ,  Hua Jin ,  Shining Zhu

Inventor： Ping Xu ,  Hua Jin ,  Shining Zhu

IPC: G02B6/12

CPC classification number: G02B6/12033 ,  G02B6/12011 ,  G02B6/12014 ,  G02B6/12016 ,  G02B6/12019 ,  G02B2006/1204 ,  G02B2006/12142 ,  G02B2006/1215 ,  G02B2006/12152 ,  G02B2006/12159 ,  G02F1/21 ,  G02F1/3775

Abstract: A photonic chip based on periodical poling and waveguides circuits in ferroelectric crystals, the method is based on the integration of waveguide circuits, periodical poling and electro-optic modulator (EOM). The chip is illustrated by FIG. 1. The waveguide circuits guide the photons and makes linear operations like the beam splitting, filtering etc. on the photons. The periodical poling enables the efficient spontaneous parametric down conversion (SPDC), resulting the generation of entangled photons. The EOM controls the phase of photons dynamically. The following directional coupler distributes the entangled photons and the quantum interference takes place, resulting different types of path-entangled states by controlling the voltage of EOM insides the chip.

Abstract translation: 基于铁电晶体周期极化和波导电路的光子芯片，该方法基于波导电路，周期极化和电光调制器（EOM）的集成。 芯片由图1示出。 波导电路引导光子并进行光子束的分光，滤光等线性运算。 周期极化使得能够有效的自发参数降低转换（SPDC），从而产生缠结的光子。 EOM动态控制光子的相位。 以下定向耦合器分配纠缠光子并发生量子干涉，通过控制EOM芯片的电压来产生不同类型的路径缠结状态。

公开(公告)号：US08492127B2

公开(公告)日：2013-07-23

申请号：US13698708

申请日：2010-11-22

Applicant: Ping Xu ,  Limin Wang ,  Bo Zhao ,  Cuiqing Ma ,  Fei Su ,  Fei Tao ,  Hongzhi Tang

Inventor： Ping Xu ,  Limin Wang ,  Bo Zhao ,  Cuiqing Ma ,  Fei Su ,  Fei Tao ,  Hongzhi Tang

IPC: C12P7/56

CPC classification number: C12N15/75 ,  C12P7/56 ,  C12P2203/00 ,  C12R1/07

Abstract: The invention is concerned with the strains of B. coagulans for lactic acid production and the related methods, in which the carbon sources are pentose or hexose or the agricultural or industrial wastes containing pentose or hexose or a mixture of both. According to the invention, the highest amount of L-lactic acid produced from glucose is 173 g/L, the optical purity is over 99%, the yield is up to 0.98, and the productivity is up to 2.4 g/L per hour. The highest amount of L-lactic acid produced from xylose is 195 g/L, the optical purity is over 99%, the yield is up to 0.98, and the productivity is up to 2.7 g/L per hour. The highest amount of L-lactic acid produced from reducing sugars in xylitol byproducts is 106 g/L, the optical purity is over 99%, and the productivity is up to 2.08 g/L per hour. The B. coagulans strains XZL4 (DSM No. 23183) and XZL9 (DSM No. 23184) of the invention can directly utilize various reducing sugars in xylitol byproducts to produce high amounts of L-lactic acid, which improves the production efficiency at low costs, and the strains are, thus, appropriate for industrial productions.

Abstract translation: 本发明涉及用于乳酸生产的凝固芽孢杆菌菌株及其相关方法，其中碳源为戊糖或己糖，或者含有戊糖或己糖的农业或工业废物或两者的混合物。 根据本发明，葡萄糖产生的L-乳酸量最高为173g / L，光学纯度超过99％，产率高达0.98，生产率高达2.4g / L。 由木糖产生的L-乳酸含量最高为195g / L，光学纯度超过99％，产率高达0.98，生产率高达2.7g / L。 由木糖醇副产物中的还原糖产生的最大量的L-乳酸为106g / L，光学纯度为99％以上，生产率高达每小时2.08g / L。 本发明的凝结芽孢杆菌菌株XZL4（DSM No.23183）和XZL9（DSM No.23184）可以直接利用木糖醇副产物中的各种还原糖来生产大量的L-乳酸，以低成本提高生产效率 ，因此适用于工业生产。

公开(公告)号：US20130029930A1

公开(公告)日：2013-01-31

申请号：US13516198

申请日：2010-12-14

Applicant: Anthony Sauve ,  Ping Xu

Inventor： Anthony Sauve ,  Ping Xu

IPC: C07C309/51 ,  C07C237/42 ,  A61K31/185 ,  C12N9/96 ,  A61K31/706

CPC classification number: C12Q1/48 ,  G01N2333/91142 ,  G01N2500/04

Abstract: The invention provides a method of increasing a deacetylated activity of SIRT6 by contacting SIRT6 with an agent that binds SIRT6 and reduces the Km of SIRT6 for a substrate, thereby increasing the deacetylase activity of SIRT6. The invention also provides compounds of the formulas (II) and (III).

Abstract translation: 本发明提供了通过使SIRT6与结合SIRT6的试剂接触并降低底物的SIRT6的Km，从而增加SIRT6的脱乙酰酶活性而提高SIRT6脱乙酰化活性的方法。 本发明还提供式（II）和（III）的化合物。

公开(公告)号：US20120148893A1

公开(公告)日：2012-06-14

申请号：US13015548

申请日：2011-01-27

Applicant: WEI-WEI ZHU ,  CHUN-BAO GU ,  MENG-PING XU ,  WEN-HSIANG HUNG

Inventor： WEI-WEI ZHU ,  CHUN-BAO GU ,  MENG-PING XU ,  WEN-HSIANG HUNG

IPC: H01M2/10

CPC classification number: H01M2/1066

Abstract: A computer enclosure includes a frame portion and a battery holding structure. The frame portion defines a battery receiving groove for receiving a battery, a first sliding groove and a second sliding groove communicating with the battery receiving groove. The battery holding structure includes a first locking member movably received in the first sliding groove, a second locking member movably received in the second sliding groove, and a spring. The first locking member includes a first latching block. The second locking member includes a second latching block. The spring is compressed between the second locking member and an inner surface of the second sliding groove and configured to provide a force to push the second latching block into the battery receiving groove. The first and second latching members can be pushed into the battery receiving groove to cooperatively latch the battery in the battery receiving groove.

Abstract translation: 计算机外壳包括框架部分和电池保持结构。 框架部分限定用于接收电池的电池接收槽，与电池容纳槽连通的第一滑动槽和第二滑动槽。 电池保持结构包括可移动地容纳在第一滑动槽中的第一锁定构件，可移动地容纳在第二滑动槽中的第二锁定构件和弹簧。 第一锁定构件包括第一锁定块。 第二锁定构件包括第二锁定块。 弹簧被压缩在第二锁定构件和第二滑动槽的内表面之间，并且构造成提供将第二闩锁块推入电池容纳槽的力。 第一和第二闩锁构件可以被推入电池容纳槽中以将电池协作地闩锁在电池容纳槽中。