公开(公告)号：US08339231B1

公开(公告)日：2012-12-25

申请号：US12729082

申请日：2010-03-22

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01F5/00 ,  H01F27/29 ,  H01F27/28

CPC classification number: H01F41/00 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A magnetics package comprising: a primary coil configured to conduct a current flow; a secondary coil electrically isolated from the primary coil and configured to conduct a current flow, wherein the secondary coil is embedded in a mold compound; and a magnetic core inductively coupling the primary coil and the secondary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Abstract translation: 一种磁性封装，包括：初级线圈，被配置为导通电流; 与所述初级线圈电隔离并且被配置为传导电流的次级线圈，其中所述次级线圈嵌入在模具化合物中; 以及感应耦合初级线圈和次级线圈的磁芯，其中初级线圈中的电流在磁芯中产生磁场，并且磁芯中的磁场在次级线圈中引起电流。

公开(公告)号：US20120181675A1

公开(公告)日：2012-07-19

申请号：US13430347

申请日：2012-03-26

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07971350B2

公开(公告)日：2011-07-05

申请号：US12221256

申请日：2008-07-31

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H05K3/30

CPC classification number: H05K9/0024 ,  H05K1/0218 ,  H05K3/284 ,  H05K3/4015 ,  H05K2201/10242 ,  H05K2203/041 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146

Abstract: A shielding assembly is configured to provide electromagnetic shielding and environmental protection to one or more electronic components coupled to a substrate. The shielding assembly includes a non-conductive mold compound layer, such as a dielectric epoxy. The mold compound layer is applied to a top surface of the substrate, thereby covering the electronic components and providing protection against environmentally induced conditions such as corrosion, humidity, and mechanical stress. The shielding assembly also includes a conductive layer applied to a top surface of the mold compound layer. The conductive layer is coupled to a ground plane in the substrate, thereby enabling the electromagnetic shielding function. The conductive layer is coupled to the ground plane via one or more metallized contacts that are coupled to the substrate and extend through the mold compound layer.

Abstract translation: 屏蔽组件被配置为向耦合到衬底的一个或多个电子部件提供电磁屏蔽和环境保护。 屏蔽组件包括非导电模制化合物层，例如电介质环氧树脂。 模具化合物层被施加到基板的顶表面，从而覆盖电子部件并且提供防止诸如腐蚀，湿度和机械应力的环境诱发条件的保护。 屏蔽组件还包括施加到模具化合物层的顶表面的导电层。 导电层耦合到衬底中的接地平面，从而实现电磁屏蔽功能。 导电层通过一个或多个金属化触点耦合到接地平面，金属化触点耦合到衬底并延伸穿过模具化合物层。

公开(公告)号：US07892884B2

公开(公告)日：2011-02-22

申请号：US12407532

申请日：2009-03-19

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块的阵列来形成硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US07821124B2

公开(公告)日：2010-10-26

申请号：US11961589

申请日：2007-12-20

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/34 ,  H01L29/76

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract translation: 公开了半导体管芯封装及其制造方法。 示例性封装包括具有源极引线和栅极引线的引线框架，以及在引线框架的第一表面处耦合到源极和栅极引线的半导体管芯。 源极引线在引线框架的第二表面具有突出区域。 模塑材料设置在半导体管芯，栅极引线和源极引线周围，使得模具的表面和突出区域的表面被模制材料暴露。 一种示例性方法包括获得半导体管芯和引线框架，以及在引线框架和管芯的至少一部分周围形成模制材料，使得突出区域的表面通过模制材料露出。

公开(公告)号：US07790513B2

公开(公告)日：2010-09-07

申请号：US12358654

申请日：2009-01-23

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

公开(公告)号：US07618896B2

公开(公告)日：2009-11-17

申请号：US11410504

申请日：2006-04-24

Applicant: Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

Inventor： Rajeev Joshi ,  Venkat Iyer ,  Jonathan Klein

IPC: H01L23/34

CPC classification number: H01L23/49575 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract translation: 公开了一种能够安装在母板上的半导体管芯封装。 半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。 半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。 基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。 第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

公开(公告)号：US20090230540A1

公开(公告)日：2009-09-17

申请号：US12407532

申请日：2009-03-19

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/488 ,  H01L21/60

CPC classification number: B23K1/0008 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract translation: 一种用于改进的多芯片半导体封装的结构和方法，其将封装电阻降低到可忽略的水平，并提供优异的热性能。 通过提供电绝缘的引线框架来促进多个管芯的外壳，该引线框架通过层压材料的非导电层与共同的基底载体分开。 在每个引线框架中形成的腔内部附着有硅管芯。 然后通过分布在每个管芯的表面以及与每个管芯相邻的引线框架的边缘的焊料凸块阵列来制造硅片的有源表面与印刷电路板的直接连接。

公开(公告)号：US20080105957A1

公开(公告)日：2008-05-08

申请号：US11961589

申请日：2007-12-20

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract translation: 本发明的实施例涉及半导体管芯封装。 本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合 （c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及 源极引线结构的主表面。

公开(公告)号：US07335532B2

公开(公告)日：2008-02-26

申请号：US11560935

申请日：2006-11-17

Applicant: Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/44

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。