公开(公告)号：US07093044B2

公开(公告)日：2006-08-15

申请号：US10971031

申请日：2004-10-25

Applicant: Joseph M Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

Inventor： Joseph M Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

IPC: G06F13/00

CPC classification number: H04L12/40058 ,  H04L12/40065 ,  H04L47/13 ,  H04L49/205

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits using the allocated isochronous channel. In a third variation, multiple receiving nodes that need to receive streaming data from a single transmitting node share a common isochronous data channel. In any of these variations, each receiver can periodically transmit a “deadman” timer message on a broadcast channel to indicate that it is still receiving on a given channel. If a transmitter detects that the deadman timer has expired, it reverts to transmitting data using a “best-efforts” scheme. A transmitter can transmit both to receivers that can handle QoS services and those that cannot explicitly support QoS services.

Abstract translation: 本发明通过具有同步数据传输能力的计算机总线提供服务质量（QoS）传递服务。 总线上的发送节点向指定的接收者发送指示所请求的连接带宽的消息。 如果预期的接收者有足够的资源，它将在总线上分配一个同步数据信道，并向发射机通知所分配的信道。 此后，发射机在分配的信道上发送数据。 如果接收者不能分配信道，则它不响应，并且发射机此后检测到超时条件，并且使用“尽力而为”的方案开始发送（即，非保证的时间传递）。 在第二变体中，接收节点检测到它正在从发送节点接收大量的数据。 作为响应，接收节点在总线上分配等时数据信道，并向发射机通知所分配的信道。 此后，发射机使用所分配的同步信道进行发射。 在第三变型中，需要从单个发射节点接收流数据的多个接收节点共享公共同步数据信道。 在这些变型中的任何一个中，每个接收机可以在广播信道上周期性地发送“死机”定时器消息，以指示它仍然在给定信道上接收。 如果发射机检测到死机定时器已经过期，则它将恢复为使用“尽力而为”方案发送数据。 发射机可以将两者传输到可以处理QoS服务的接收机和不能明确支持QoS服务的接收机。

公开(公告)号：US06952797B1

公开(公告)日：2005-10-04

申请号：US09696666

申请日：2000-10-25

Applicant: Andy Kahn ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Steven R. Kleiman

Inventor： Andy Kahn ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Steven R. Kleiman

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/09 ,  G11C29/00 ,  H03M13/00

CPC classification number: G06F11/1076 ,  G11B20/18 ,  H03M13/096

Abstract: A method and apparatus for a reliable data storage system using block level checksums appended to data blocks. Files are stored on hard disks in storage blocks, including data blocks and block-appended checksums. The block-appended checksum includes a checksum of the data block, a VBN, a DBN, and an embedded checksum for checking the integrity of the block-appended checksum itself. A file system includes file blocks with associated block-appended checksum to the data blocks. The file blocks with block-appended checksums are written to storage blocks. In a preferred embodiment a collection of disk drives are formatted with 520 bytes of data per sector. For each 4,096-byte file block, a corresponding 64-byte block-appended checksum is appended to the file block with the first 7 sectors including most of the file block data while the 8th sector includes the remaining file block data and the 64-byte block-appended checksum.

Abstract translation: 一种使用附加到数据块的块级校验和的可靠数据存储系统的方法和装置。 文件存储在存储块中的硬盘上，包括数据块和块附加校验和。 块附加的校验和包括数据块的校验和，VBN，DBN和用于检查块附加校验和本身的完整性的嵌入校验和。 文件系统包括具有与数据块相关联的块附加校验和的文件块。 具有块附加校验和的文件块被写入存储块。 在优选实施例中，磁盘驱动器的集合被格式化为每扇区520字节的数据。 对于每个4,096字节的文件块，相应的64字节的块附加校验和被附加到文件块，前7个扇区包括大部分文件块数据，而第8个扇区包括剩余的 文件块数据和64字节的块附加校验和。

公开(公告)号：US06944065B2

公开(公告)日：2005-09-13

申请号：US10877634

申请日：2004-06-25

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US20050080947A1

公开(公告)日：2005-04-14

申请号：US10971031

申请日：2004-10-25

Applicant: Joseph Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

Inventor： Joseph Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

IPC: G06F13/00 ,  H04L12/40 ,  H04L12/56 ,  H04L12/64

CPC classification number: H04L12/40058 ,  H04L12/40065 ,  H04L47/13 ,  H04L49/205

Abstract: The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits using the allocated isochronous channel. In a third variation, multiple receiving nodes that need to receive streaming data from a single transmitting node share a common isochronous data channel. In any of these variations, each receiver can periodically transmit a “deadman” timer message on a broadcast channel to indicate that it is still receiving on a given channel. If a transmitter detects that the deadman timer has expired, it reverts to transmitting data using a “best-efforts” scheme. A transmitter can transmit both to receivers that can handle QoS services and those that cannot explicitly support QoS services.

Abstract translation: 本发明通过具有同步数据传输能力的计算机总线提供服务质量（QoS）传递服务。 总线上的发送节点向指定的接收者发送指示所请求的连接带宽的消息。 如果预期的接收者有足够的资源，它将在总线上分配一个同步数据信道，并向发射机通知所分配的信道。 此后，发射机在分配的信道上发送数据。 如果接收者不能分配信道，则它不响应，并且发射机此后检测到超时条件，并且使用“尽力而为”的方案开始发送（即，非保证的时间传递）。 在第二变体中，接收节点检测到它正在从发送节点接收大量的数据。 作为响应，接收节点在总线上分配等时数据信道，并向发射机通知所分配的信道。 此后，发射机使用所分配的同步信道进行发射。 在第三变型中，需要从单个发射节点接收流数据的多个接收节点共享公共同步数据信道。 在这些变型中的任何一个中，每个接收机可以在广播信道上周期性地发送“死机”定时器消息，以指示它仍然在给定信道上接收。 如果发射机检测到死机定时器已经过期，则它将恢复为使用“尽力而为”方案发送数据。 发射机可以将两者传输到可以处理QoS服务的接收机和不能明确支持QoS服务的接收机。

公开(公告)号：US06799284B1

公开(公告)日：2004-09-28

申请号：US09797007

申请日：2001-02-28

Applicant: Kayuri Patel ,  Raymond Chen ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Andy Kahn

Inventor： Kayuri Patel ,  Raymond Chen ,  Rajesh Sundaram ,  Srinivasan Viswanathan ,  Andy Kahn

IPC: G06F1100

CPC classification number: G06F11/1076

Abstract: The invention provides a method and system for reducing RAID parity computation following a RAID subsystem failure. Ranges of RAID stripes are assigned to bits in a bitmap that is stored on disk. When writes to the RAID are in progress, the bit associated with the range of stripes in the bitmap is set. When a failure occurs during the write process, the bitmap is analyzed on reboot to determine which ranges of stripes where in the process of being written, and the parity data for only those ranges of stripes is recomputed. Efficiency is increased by use of an in-memory write counter that tracks multiple writes to each stripe range. Using the write counter, the bitmap is written to disk only after each cycle of its associated bitmap bit being set to a value of 1 and then returning to zero. The invention may be installed, modified, and removed at will from a RAID array, and this may be accomplished while the system is in operation.

Abstract translation: 本发明提供了一种用于在RAID子系统故障之后减少RAID奇偶校验计算的方法和系统。 RAID条带的范围分配给存储在磁盘上的位图中的位。 当对RAID的写入进行中，与位图中的条带范围相关联的位被设置。 当在写入过程中发生故障时，在重新启动时分析位图，以确定在写入过程中哪个条带范围，并且仅重新计算那些条带范围的奇偶校验数据。 通过使用跟踪对每个条带范围的多次写入的内存中写计数器来提高效率。 使用写计数器，位图仅在其相关位图位的每个周期设置为1，然后返回到零后才写入磁盘。 本发明可以随意地从RAID阵列安装，修改和移除，并且这可以在系统运行时完成。

公开(公告)号：US06629047B1

公开(公告)日：2003-09-30

申请号：US09539475

申请日：2000-03-30

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

IPC: G11C1300

CPC classification number: G11C5/147 ,  G11C16/225

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract translation: 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

公开(公告)号：US06477091B2

公开(公告)日：2002-11-05

申请号：US09823463

申请日：2001-03-30

Applicant: Kerry D. Tedrow ,  Rajesh Sundaram

Inventor： Kerry D. Tedrow ,  Rajesh Sundaram

IPC: G11C700

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地说，本发明的实施例可以在耦合到待擦除的存储器单元时提供用于擦除的负电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不耦合到被选择被擦除的存储器单元时，几乎没有电流消耗。

公开(公告)号：US09354989B1

公开(公告)日：2016-05-31

申请号：US13251916

申请日：2011-10-03

Applicant: Priya Sehgal ,  Kaladhar Voruganti ,  Rajesh Sundaram

Inventor： Priya Sehgal ,  Kaladhar Voruganti ,  Rajesh Sundaram

IPC: G06F12/08 ,  G06F12/00 ,  G06F11/14

CPC classification number: G06F11/1482 ,  G06F11/00

Abstract: Region based admission and eviction control can be used for managing resources (e.g., caching resources) shared by competing workloads with different SLOs in hybrid aggregates. A “region” or “phase” refers to different incoming loads of a workload (e.g., different working set sizes, different intensities of the workload, etc.). These regions can be identified and then utilized along with other factors (e.g., incoming loads of other workloads, maximum cache allocation size, service level objectives, and others factors/parameters) in managing cache storage resources.

Abstract translation: 基于区域的准入和撤离控制可用于管理与混合聚合中的不同SLO的竞争工作负载共享的资源（例如，缓存资源）。 “区域”或“相位”是指工作负载的不同输入负载（例如，不同的工作集大小，工作负载的不同强度等）。 这些区域可以在管理高速缓存存储资源中被识别并随后与其他因素（例如，其他工作负载的进入负载，最大缓存分配大小，服务水平目标和其他因素/参数）一起使用。

公开(公告)号：US09195589B2

公开(公告)日：2015-11-24

申请号：US13977084

申请日：2011-12-27

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Blaise Fanning

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Blaise Fanning

IPC: G06F3/00 ,  G06F12/02 ,  G06F9/30 ,  G06F1/32 ,  G11C16/06

CPC classification number: G11C13/0038 ,  G06F1/3275 ,  G06F9/30101 ,  G06F12/0246 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/06 ,  Y02D10/14

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Abstract translation: 公开了用于非易失性存储器的自适应配置的示例。 示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。 这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。

公开(公告)号：US20150269100A1

公开(公告)日：2015-09-24

申请号：US14731183

申请日：2015-06-04

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract translation: 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。