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    TRANSPORT BRIDGE AND PROTOCOL DEVICE FOR EFFICIENT PROCESSING IN A DATA STORAGE ENVIRONMENT
    41.
    发明公开
    TRANSPORT BRIDGE AND PROTOCOL DEVICE FOR EFFICIENT PROCESSING IN A DATA STORAGE ENVIRONMENT 审中-公开

    公开(公告)号：US20230418516A1

    公开(公告)日：2023-12-28

    申请号：US17848151

    申请日：2022-06-23

    Applicant: Seagate Technology, LLC

    Inventor： Richard O. Weiss ,  Jason Matthew Feist ,  Steven Williams ,  Hemant Vitthalrao Mane

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0619 ,  G06F3/0689

    Abstract: Apparatus and method for servicing data transfer commands in a computer environment using a selected protocol such as NVMe (Non-Volatile Memory Express). In some embodiments, a secure connection is established between a client device and a bridge device across an interface. A controller of the bridge device presents a unitary namespace as an available memory space to the client device. The controller further communicates with a plurality of downstream target devices to allocate individual namespaces within main memory stores of each of the target devices to form a consolidated namespace to support the unitary namespace presented to the controller. In this way, the bridge device can operate as an NVMe controller with respect to the client device for the unitary namespace, and as a virtual client device to each of the target devices which operate as embedded NVMe controllers for the individual namespaces.

    Ordering reads to limit collisions in a non-volatile memory (NVM)
    43.
    发明授权
    Ordering reads to limit collisions in a non-volatile memory (NVM) 有权

    公开(公告)号：US11822817B2

    公开(公告)日：2023-11-21

    申请号：US17443554

    申请日：2021-07-27

    Applicant: Seagate Technology LLC

    Inventor： Christopher Smith

    IPC: G06F3/06 ,  G06F12/0875 ,  G06F12/0804

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/0804 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/2022

    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a data storage device includes a main non-volatile memory (NVM), a host command queue that lists pending host read and host write commands, and a write cache which temporarily stores write data sets pending transfer to the NVM responsive to execution of the associated host write commands in the host command queue. A collision prediction circuit predicts a rate of future collisions involving the cached write data sets. A storage manager directs storage of the write data sets to a first target location responsive to the rate of future collisions being at a first level, and directs storage of the write data sets to a different, second target location responsive to the rate of future collisions being at a different, second level.

    IDLE POWER SAVING FOR ACTUATOR DEVICE
    45.
    发明公开
    IDLE POWER SAVING FOR ACTUATOR DEVICE 审中-公开

    公开(公告)号：US20230360676A1

    公开(公告)日：2023-11-09

    申请号：US17735380

    申请日：2022-05-03

    Applicant: Seagate Technology LLC

    Inventor： Tze Ming Pang ,  MingZhong Ding ,  ChanFan Lau ,  Chi Sern Tan ,  Ye HaiBo

    IPC: G11B19/04 ,  G11B5/48

    CPC classification number: G11B19/047 ,  G11B5/4813 ,  G11B5/486

    Abstract: Systems and methods are disclosed for an actuator device or actuator control device to implement a low power savings mode. For example, a device can comprise an actuator arm including a first actuator and a second actuator, the second actuator configured to refine a movement of the actuator arm to a more precise position than use of merely the first actuator. A device can also comprise a control system configured to determine when the device is in an idle state and, when the device is in the idle state, disable the second actuator and perform a positional seek operation with the second actuator disabled. Power savings can occur from disabling the second actuator, which may also include disabling associated circuitry, such that it does not consume power or consumes a nominal (e.g., negligible or insignificant) amount of power during the associated seek operation.

    Maintaining real-time cache coherency during distributed computational functions
    48.
    发明授权
    Maintaining real-time cache coherency during distributed computational functions 有权

    公开(公告)号：US11809323B1

    公开(公告)日：2023-11-07

    申请号：US17846388

    申请日：2022-06-22

    Applicant: Seagate Technology LLC

    Inventor： Marc Timothy Jones ,  David Jerome Allen ,  Steven Williams ,  Jason Matthew Feist

    IPC: G06F12/0815 ,  G06F12/0817

    CPC classification number: G06F12/0828 ,  G06F12/0815 ,  G06F2212/621

    Abstract: Apparatus and method for maintaining real-time coherency between a local cache of a target device and a client cache of a source device during execution of a distributed computational function. In some embodiments, a source device, such as a host computer, is coupled via a network interface to a target device, such as a data storage device. A storage compute function (SCF) command is transferred from the source device to the target device. A local cache of the target device accumulates output data during the execution of an associated SCF over an execution time interval. Real-time coherency is maintained between the contents of the local cache and a client cache of the source device, so that the client cache retains continuously updated copies of the contents of the local cache during execution of the SCF. The coherency can be carried out on a time-based granularity or an operational granularity.

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