公开(公告)号：US06207490B1

公开(公告)日：2001-03-27

申请号：US09209993

申请日：1998-12-10

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L218242

CPC classification number: H01L21/28114 ,  H01L21/28132 ,  H01L21/823437 ,  H01L27/1052 ,  H01L29/42376

Abstract: There are provided a semiconductor device and a fabricating method thereof, in which a plurality of buried diffusion layers repeatedly extend on a semiconductor substrate and a plurality of word lines repeatedly extend on the buried diffusion layers, perpendicularly to the buried diffusion layers. The cross-sections of the word lines are shaped in asymmetrical polygons, with odd-numbered word lines having the same cross-section and the even-numbered word lines having the same cross-section. Narrow gate electrodes can be formed on the buried diffusion layers, using a spacer mask, so that the area of a memory cell array can be reduced by 50% and thus a cell integration level can be increased.

Abstract translation: 提供了一种半导体器件及其制造方法，其中多个掩埋扩散层在半导体衬底上重复延伸，并且多个字线在掩埋扩散层上重叠地延伸，垂直于埋入扩散层。 字线的横截面成形为不对称多边形，奇数字线具有相同的横截面，偶数字线具有相同的横截面。 可以使用间隔掩模在掩埋扩散层上形成窄栅电极，使得存储单元阵列的面积可以减少50％，从而可以提高单元集成度。

公开(公告)号：US08836020B2

公开(公告)日：2014-09-16

申请号：US13285291

申请日：2011-10-31

Applicant: Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

Inventor： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC: H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract translation: 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US20140197546A1

公开(公告)日：2014-07-17

申请号：US14156827

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

Inventor： Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract translation: 垂直型半导体器件中的阶形形状焊盘结构和布线结构包括具有第一线形状并且在边缘部分的上表面处包括第一焊盘区域的第一导线和具有第二线形并且间隔开的第二导线 并且设置在第一导线上。 第一导线的端部延伸到第一位置。 第二焊盘区域包括在第二导线的边缘部分的上表面上。 第二导线的端部延伸到第一位置。 第二导电线包括在垂直方向上与第一焊盘区域相对的部分处的凹部，以露出第一焊盘区域。 衬垫结构可以用在垂直型非易失性存储器件中。

公开(公告)号：US20130168800A1

公开(公告)日：2013-07-04

申请号：US13717803

申请日：2012-12-18

Applicant: Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

Inventor： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

IPC: H01L29/06

CPC classification number: H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract translation: 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

公开(公告)号：US20120270376A1

公开(公告)日：2012-10-25

申请号：US13542777

申请日：2012-07-06

Applicant: Dongyean Oh ,  Woon-kyung Lee

Inventor： Dongyean Oh ,  Woon-kyung Lee

IPC: H01L21/8232

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823493

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US20120074484A1

公开(公告)日：2012-03-29

申请号：US13223698

申请日：2011-09-01

Applicant: Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

Inventor： Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L21/764 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11526

Abstract: A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成彼此间隔开的多个栅极结构; 形成覆盖所述栅极结构的第一绝缘层，所述第一绝缘层包括所述栅极结构之间的空隙; 去除所述第一绝缘层的上部以在所述栅极结构的下部的侧壁和所述栅极结构之间的所述衬底上形成第一绝缘层图案，所述第一绝缘层图案包括其上的第一凹部; 在由第一绝缘层图案暴露的栅极结构的上部形成导电层; 使导电层与栅极结构反应; 以及在所述栅极结构的上部形成第二绝缘层，所述第二绝缘层包括与所述第一凹部流体连通的第二凹部。

公开(公告)号：US20110059585A1

公开(公告)日：2011-03-10

申请号：US12943366

申请日：2010-11-10

Applicant: Woon-Kyung LEE ,  Jeong-Hyuk CHOI

Inventor： Woon-Kyung LEE ,  Jeong-Hyuk CHOI

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

Abstract translation: 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。

公开(公告)号：US07851304B2

公开(公告)日：2010-12-14

申请号：US11641869

申请日：2006-12-20

Applicant: Woon-Kyung Lee ,  Jeong-Hyuk Choi

Inventor： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

Abstract translation: 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。

公开(公告)号：US20080096350A1

公开(公告)日：2008-04-24

申请号：US11641869

申请日：2006-12-20

Applicant: Woon-Kyung Lee ,  Jeong-Hyuk Choi

Inventor： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

Abstract translation: 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。

公开(公告)号：US20080079038A1

公开(公告)日：2008-04-03

申请号：US11646127

申请日：2006-12-27

Applicant: Tae-Kyung Kim ,  Woon-Kyung Lee

Inventor： Tae-Kyung Kim ,  Woon-Kyung Lee

IPC: H01L29/76

CPC classification number: H01L21/2652 ,  H01L21/28123 ,  H01L21/28238 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368

Abstract: Methods of forming a semiconductor device include an active region and a shallow trench isolation region in a semiconductor substrate, and forming a gate insulation layer on the active region. The gate insulation layer includes a first part spaced apart from the shallow trench isolation region and a second part adjacent the shallow trench isolation region and disposed between the shallow trench isolation region and the first part, and thicker than the first part. The methods further include forming a first impurity region in the active region of the semiconductor substrate adjacent the first part, and forming a gate line on the gate insulation layer. Corresponding semiconductor devices are also disclosed.

Abstract translation: 形成半导体器件的方法包括半导体衬底中的有源区和浅沟槽隔离区，并且在有源区上形成栅极绝缘层。 栅极绝缘层包括与浅沟槽隔离区域间隔开的第一部分和与浅沟槽隔离区域相邻并且设置在浅沟槽隔离区域和第一部分之间并且比第一部分更厚的第二部分。 所述方法还包括在所述半导体衬底的与所述第一部分相邻的有源区中形成第一杂质区，以及在所述栅极绝缘层上形成栅极线。 还公开了相应的半导体器件。