公开(公告)号：US11972140B2

公开(公告)日：2024-04-30

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230063676A1

公开(公告)日：2023-03-02

申请号：US17657524

申请日：2022-03-31

Applicant: Apple Inc.

Inventor： Sagi Lahav ,  Lital Levy - Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

IPC: G06F9/46 ,  G06F9/32 ,  G06F9/50 ,  G06F9/30

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

公开(公告)号：US20230058989A1

公开(公告)日：2023-02-23

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasan Rangan Sridharan

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US10769065B2

公开(公告)日：2020-09-08

申请号：US16436635

申请日：2019-06-10

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Charles E. Tucker ,  Jeffry E. Gonion ,  Gerard R. Williams, III ,  Chris Cheng-Chieh Lee

IPC: H03M7/00 ,  G06F12/08 ,  H03M7/30 ,  G06F12/0886 ,  G06F12/00 ,  G06F13/00

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

公开(公告)号：US10401945B2

公开(公告)日：2019-09-03

申请号：US15935274

申请日：2018-03-26

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, Jr. ,  Richard F. Russo

IPC: G06F1/32 ,  G06F1/3293 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/50

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

公开(公告)号：US20180232034A1

公开(公告)日：2018-08-16

申请号：US15430699

申请日：2017-02-13

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F1/32

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

公开(公告)号：US09958932B2

公开(公告)日：2018-05-01

申请号：US14548912

申请日：2014-11-20

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, Jr. ,  Richard F. Russo

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

公开(公告)号：US09223577B2

公开(公告)日：2015-12-29

申请号：US13627884

申请日：2012-09-26

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

Abstract: Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

Abstract translation: 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。

公开(公告)号：US09043554B2

公开(公告)日：2015-05-26

申请号：US13725066

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Perumal R. Subramoniam ,  Pradeep Kanapathipillai

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/0888

Abstract: Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit. Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.

Abstract translation: 用于保持不可缓存的数据一致的系统，处理器和方法。 处理器包括多级缓存层次结构，并且不可缓存的加载存储器操作可以在高速缓存层级的任何级别缓存。 如果L2缓存中存在不可缓存的加载错误，则不可缓存的加载的分配将被限制为L2高速缓存的一部分。 如果不可缓存的存储器操作命中在L1缓存中，则命中高速缓存行可以用来自存储器操作的数据来更新。 如果不可缓存的商店在L1缓存中丢失，则不可缓存的商店被发送到核心接口单元。 在发送到L2缓存之前，多个连续的存储器缺失在核心接口单元中被合并到更大的数据块中。

公开(公告)号：US09015422B2

公开(公告)日：2015-04-21

申请号：US13942780

申请日：2013-07-16

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Gerard R. Williams, III ,  Hari S. Kannan ,  Pavlos Konas

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026 ,  Y02D10/13

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetcher in which patterns may include wild cards for some cache blocks. The wild card may match any access for the corresponding cache block (e.g. no access, demand access, prefetch, successful prefetch, etc.). Furthermore, patterns with irregular strides and/or irregular access patterns may be included in the matching patterns and may be detected for prefetch generation. In an embodiment, the AMPM prefetcher may implement a chained access map for large streaming prefetches. If a stream is detected, the AMPM prefetcher may allocate a pair of map entries for the stream and may reuse the pair for subsequent access map regions within the stream. In some embodiments, a quality factor may be associated with each access map and may control the rate of prefetch generation.

Abstract translation: 在一个实施例中，处理器可以实现基于访问映射模式匹配（AMPM）的预取器，其中模式可以包括一些高速缓存块的通配符。 通配符可以匹配对应的高速缓存块的任何访问（例如，无访问，请求访问，预取，成功预取等）。 此外，具有不规则步幅和/或不规则访问模式的模式可以被包括在匹配模式中，并且可以被检测用于预取生成。 在一个实施例中，AMPM预取器可以实现用于大型流预取的链接访问映射。 如果检测到流，则AMPM预取器可以为流分配一对映射条目，并且可以将该对重新使用在该流内的后续访问映射区域。 在一些实施例中，质量因子可以与每个访问映射关联，并且可以控制预取生成的速率。