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    Digital forward body biasing in CMOS circuits
    41.
    发明授权
    Digital forward body biasing in CMOS circuits 有权

    公开(公告)号：US10181848B2

    公开(公告)日：2019-01-15

    申请号：US15418331

    申请日：2017-01-27

    Applicant: ARM Limited

    Inventor： Pranay Prabhat ,  Parameshwarappa Anand Kumar Savanth ,  James Edward Myers

    IPC: H03K17/687 ,  H01L29/10

    Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

    Monitoring Circuit and Method
    42.
    发明申请
    Monitoring Circuit and Method 审中-公开

    公开(公告)号：US20180150120A1

    公开(公告)日：2018-05-31

    申请号：US15361405

    申请日：2016-11-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar Savanth ,  Bal S. Sandhu ,  James Edward Myers ,  Alexander Stewart Weddell ,  David Walter Flynn

    IPC: G06F1/28 ,  G01R19/165

    CPC classification number: G06F1/28 ,  G01R19/16576

    Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

    Flip-flop
    43.
    发明授权
    Flip-flop 有权

    公开(公告)号：US09985613B2

    公开(公告)日：2018-05-29

    申请号：US15336721

    申请日：2016-10-27

    Applicant: ARM Limited ,  University of Southampton

    Inventor： Anand Savanth ,  James Edward Myers ,  Yunpeng Cai ,  Alexander Stewart Weddell ,  Tom Kazmierski

    IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/20

    CPC classification number: H03K3/35625 ,  H03K19/20

    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

    Brown-Out Detector
    46.
    发明申请
    Brown-Out Detector 审中-公开
    欠压检测器

    公开(公告)号：US20160334470A1

    公开(公告)日：2016-11-17

    申请号：US14712614

    申请日：2015-05-14

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  James Edward Myers

    IPC: G01R31/40 ,  G01R19/165 ,  G01R19/32 ,  G01R17/00

    CPC classification number: G06F1/28 ,  G01R19/16552 ,  G01R19/32

    Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

    Abstract translation: 本文描述的各种实现涉及用于欠压检测的集成电路。 集成电路可以包括第一级，其被配置为接收输入电压并提供独立于温度的第一电压，同时保持与输入电压相关。 集成电路可以包括被配置为接收输入电压的第二级，从第一级接收第一电压，并且当输入电压降低时上变换第一电压。 第二级可以被配置为提供对应于输入电压和第一电压的差分电压的第二电压。 集成电路可以包括被配置为接收第二电压并且提供对应于误差信号的高增益输出电压的第三级。

    Integrated circuit device, system and method
    48.
    发明授权
    Integrated circuit device, system and method 有权

    公开(公告)号：US12124384B2

    公开(公告)日：2024-10-22

    申请号：US17817686

    申请日：2022-08-05

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  Shidhartha Das

    IPC: G06F21/72 ,  G01R31/28 ,  G01R31/303 ,  G06F12/14 ,  G06F21/60 ,  G11C29/12 ,  H01L21/66

    CPC classification number: G06F12/1408 ,  G06F21/72 ,  G06F2212/1052

    Abstract: An integrated circuit device including processing circuitry, communications circuitry configured to provide a communication link with a communication apparatus external to the integrated circuit device, and a memory accessible by the processing circuitry and by the communications circuitry, the memory comprising a memory region to which the processing circuitry has write access and to which the communications circuitry has read access, in which the processing circuitry is configured to write information to the memory region indicative of one or more use conditions of the integrated circuit device, and in which the communications circuitry is configured to access the memory region and to provide the information indicative of the one or more use conditions of the integrated circuit device via the communication link.

    Methods and apparatus for electronic voting
    50.
    发明授权
    Methods and apparatus for electronic voting 有权

    公开(公告)号：US11587386B1

    公开(公告)日：2023-02-21

    申请号：US17390436

    申请日：2021-07-30

    Applicant: Arm Limited

    Inventor： Emre Özer ,  James Edward Myers ,  Jedrzej Kufel ,  John Philip Biggs ,  Remy Pottier

    IPC: G06K19/02 ,  G07C13/02 ,  G06K19/077 ,  G06K7/08 ,  H05K1/16 ,  H05K1/03 ,  H05K3/12 ,  G06Q90/00

    Abstract: Aspects of the present disclosure relate to an apparatus comprising: a substrate; communication circuitry deposited on said substrate; and ballot circuitry deposited on said substrate. The ballot circuitry comprises: a plurality of voting circuitry elements, each voting circuitry element being responsive to a voting operation to change a conductive state of that voting circuitry element; and logic circuitry communicatively coupled with each of the plurality of voting circuitry elements and with the communication circuitry. The logic circuitry is configured to: detect the conductive state of each of the plurality of voting circuitry elements; and transmit, via the communication circuitry and based on the conductive state of each of the plurality of voting circuitry elements, a voting result.

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