公开(公告)号：US20220318161A1

公开(公告)日：2022-10-06

申请号：US17219273

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Indrani Paul ,  Jean J. Chittilappilly ,  Abhishek Kumar Verma ,  James R. Magro ,  Kavyashree Pilar

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/406

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

公开(公告)号：US20220091784A1

公开(公告)日：2022-03-24

申请号：US17027375

申请日：2020-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F3/06

Abstract: A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.

公开(公告)号：US20220028450A1

公开(公告)日：2022-01-27

申请号：US16938855

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C11/406 ,  G06F1/3203 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11221772B2

公开(公告)日：2022-01-11

申请号：US16241716

申请日：2019-01-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas H. Hamilton

IPC: G06F3/06 ,  G11C5/14 ,  G11C11/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C29/04

Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.

公开(公告)号：US10403333B2

公开(公告)日：2019-09-03

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G06F12/1018 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US20180088862A1

公开(公告)日：2018-03-29

申请号：US15274178

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Glennis Eliagh Covington ,  Kevin M. Brandl ,  Nienchi Hu ,  Shannon T. Kesner

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C5/04 ,  G11C7/00 ,  G11C29/026 ,  G11C29/028

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.

公开(公告)号：US20150078104A1

公开(公告)日：2015-03-19

申请号：US14497977

申请日：2014-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。