公开(公告)号：US20070013351A1

公开(公告)日：2007-01-18

申请号：US11485466

申请日：2006-07-13

申请人： Toshiyuki Naka ,  Akio Nakagawa ,  Kazutoshi Nakamura

发明人： Toshiyuki Naka ,  Akio Nakagawa ,  Kazutoshi Nakamura

IPC分类号： G05F1/00

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.

摘要翻译： 电子功率单元包括第一和第二MOS晶体管和数字控制电路。 第一个MOS晶体管向负载施加电压。 第二MOS晶体管保持导通，而第一MOS晶体管保持关断并且对负载中流动的电流进行整流。 数字控制电路在从第二MOS晶体管截止时起第一时间间隔开启第一晶体管。 数字控制电路在从第一MOS晶体管截止时经过第二时间间隔开启第二MOS晶体管。 数字控制电路控制第一MOS晶体管的导通周期，使得施加到负载的电压在不连续导通模式下是恒定的。 数字控制电路在施加到负载的电压是恒定的情况下确定第一次从占空比的最佳值。

公开(公告)号：US07026214B2

公开(公告)日：2006-04-11

申请号：US10957692

申请日：2004-10-05

申请人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Norio Yasuhara ,  Syotaro Ono ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L21/00

CPC分类号： H01L29/402 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

公开(公告)号：USRE38907E1

公开(公告)日：2005-12-06

申请号：US10452203

申请日：2003-06-02

申请人： Tomoko Matsudai ,  Tsutomu Kojima ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Tsutomu Kojima ,  Akio Nakagawa

IPC分类号： H03K5/22 ,  H03K5/24 ,  H03K17/082 ,  H03K17/10 ,  H03K17/14

CPC分类号： H03K17/102 ,  H03K5/2481 ,  H03K17/0828 ,  H03K17/145

摘要： The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.

摘要翻译： 比较器电路的差分放大器包括用于接收输入信号的第一和第二n型MOSFET，电流镜电路的第一和第二p型MOSFET以及电流源电路的第三n型MOSFET。 输出级包括用于传输信号的第三p型MOSFET和电流源电路的第四n型MOSFET。 差分放大器还包括分别串联连接到第一和第二n型MOSFET的第五和第六n型MOSFET。 输出级还包括与第四n型MOSFET串联连接的第七n型MOSFET。 第五，第六和第七n型MOSFET的栅极连接到电压偏置电路。 第五，第六和第七n型MOSFET抑制由于第一，第二和第四主n型MOSFET的饱和特性不良引起的输出节点的电压变化。

公开(公告)号：US06705574B2

公开(公告)日：2004-03-16

申请号：US10238721

申请日：2002-09-11

申请人： Akio Nakagawa ,  Tetsuzo Nakazawa ,  Takashi Sato ,  Takaki Tsutsui

发明人： Akio Nakagawa ,  Tetsuzo Nakazawa ,  Takashi Sato ,  Takaki Tsutsui

IPC分类号： F16L300

CPC分类号： H01R13/5816

摘要： In a cable mounting structure, a casing body is formed with a through hole through which a cable is inserted. A first retainer is secured to a first part of the cable and fitted with the through hole. A second retainer is attached on the casing body while holding a second part of the cable. The first retainer is an elastic member having a groove fitted with an edge of the through hole. The second retainer includes a retaining member provided on the casing body while being formed with a guide groove, and a holding member detachably fitted into the guide groove.

摘要翻译： 在电缆安装结构中，壳体形成有电缆插入通孔。 第一保持器固定到电缆的第一部分并且装配有通孔。 在保持电缆的第二部分的同时，第二保持器附接在壳体上。 第一保持器是具有与通孔的边缘配合的槽的弹性构件。 第二保持器包括设置在壳体上的保持构件，同时形成有引导槽，并且保持构件可拆卸地装配到引导槽中。

公开(公告)号：US06683343B2

公开(公告)日：2004-01-27

申请号：US10084051

申请日：2002-02-28

申请人： Tomoko Matsudai ,  Akio Nakagawa

发明人： Tomoko Matsudai ,  Akio Nakagawa

IPC分类号： H01L2976

CPC分类号： H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

摘要： In an IGBT, an n buffer layer is formed under an n− high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain layer is doped at a low dose, the efficiency of carrier injection can be reduced and a high-speed operation is possible without lifetime control. Since no lifetime control is performed, the on-state voltage can be low. Since the n buffer layer does not immediately stop the extension of the depletion layer during a turn-off period, oscillation of the current and voltage is prevented. The n+ buffer layer maintains a sufficient withstand voltage when a reverse bias is applied.

摘要翻译： 在IGBT中，n型缓冲层形成在形成有MOS栅极结构的n +高电阻层的下方。 在n缓冲层和p +漏极层之间形成n + +缓冲层。 由于p +漏极层以低剂量掺杂，所以可以降低载流子注入的效率，并且可以在没有寿命的情况下进行高速操作。 由于不进行寿命控制，因此导通电压可以低。 由于n缓冲层在关断期间不会立即停止耗尽层的延伸，所以防止了电流和电压的振荡。 当施加反向偏压时，n + +缓冲层保持足够的耐受电压。

公开(公告)号：US5689121A

公开(公告)日：1997-11-18

申请号：US480389

申请日：1995-06-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5536961A

公开(公告)日：1996-07-16

申请号：US396794

申请日：1995-03-01

申请人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Akio Nakagawa ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/404 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/402 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286

摘要： A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

公开(公告)号：US5443524A

公开(公告)日：1995-08-22

申请号：US73418

申请日：1993-06-09

申请人： Seishi Sawamura ,  Sakuya Nakajima ,  Kunio Amemori ,  Hidehisa Oku ,  Akio Nakagawa ,  Ichiro Kitayama ,  Mikio Yuki ,  Shiro Horiguchi ,  Yoshihisa Araki ,  Shigeru Yuki ,  Toshihiro Hamada

发明人： Seishi Sawamura ,  Sakuya Nakajima ,  Kunio Amemori ,  Hidehisa Oku ,  Akio Nakagawa ,  Ichiro Kitayama ,  Mikio Yuki ,  Shiro Horiguchi ,  Yoshihisa Araki ,  Shigeru Yuki ,  Toshihiro Hamada

IPC分类号： A61F2/64 ,  A61F2/68 ,  A61F2/70 ,  A61F2/72 ,  A61F2/74

CPC分类号： A61F2/68 ,  A61F2/64 ,  A61F2/70 ,  A61F2002/705 ,  A61F2002/747

摘要： The present invention is intended to provide a teaching playback swing-phase-controlled above knee prosthesis which enables an external data setting to set the mechanism of the teaching playback swing-phase-controlled above knee prosthesis for conditions that enable the mechanism to operate for motions according to a walking speed. The teaching playback swing-phase-controlled above knee prosthesis includes a structural body having a thigh frame and a leg frame pivotally joined to the thigh frame for swing motion relative to the thigh frame, an air cylinder having a cylinder body, a piston axially slidably fitted in the cylinder body and provided with a valve, and a piston rod having one end fixed to the piston and the other end pivotally joined to the thigh frame, and a stepping motor for adjusting the opening of the valve of the cylinder. The opening of the valve of the cylinder is adjusted by the stepping motor to regulate sliding speed of the piston by adjusting the resistance against the flow of air through the valve so that the leg frame is able to swing relative to the thigh frame properly according to a predetermined walking speed. Data concerning the opening of the valve is taught to the teaching playback swing-phase-controlled above knee prosthesis by signals sent out by an external data setting device.

摘要翻译： 本发明旨在提供一种教学重放摆动相位控制的膝关节假体，其使得外部数据设置能够将使得该机构能够运动的条件的条件设定在膝关节假体上方的摆动相位控制的回放机构 根据步行速度。 在膝关节假体上方的回放摆动相控制的教学回放包括具有大腿框架和枢转地连接到大腿框架以相对于大腿框架摆动的腿架的结构体，气缸，具有缸体，活塞可轴​​向滑动 安装在缸体中并设置有阀，以及活塞杆，其一端固定到活塞，另一端枢转地连接到大腿架;以及步进电机，用于调节气缸的阀的开度。 通过步进电机调节气缸阀门的开度，通过调节抵抗通过阀门的空气流动的阻力来调节活塞的滑动速度，使得腿架能够相对于大腿架适当地摆动，根据 预定行走速度。 通过由外部数据设定装置发出的信号，教导了关于阀的打开的数据。

公开(公告)号：US5381026A

公开(公告)日：1995-01-10

申请号：US760344

申请日：1991-09-16

申请人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

IPC分类号： H01L29/423 ,  H01L29/745 ,  H01L29/749 ,  H01L27/08 ,  H01L29/74

CPC分类号： H01L29/7455 ,  H01L29/42308 ,  H01L29/749

摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

公开(公告)号：US5210432A

公开(公告)日：1993-05-11

申请号：US615252

申请日：1990-11-19

申请人： Takashi Shinohe ,  Masaki Atsuta ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Masaki Atsuta ,  Akio Nakagawa

IPC分类号： H01L29/744 ,  H01L29/08 ,  H01L29/74 ,  H01L29/749

CPC分类号： H01L29/0839

摘要： According to this invention, there is disclosed an insulated gate GTO thyristor comprising a pnpn structure including a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. The thyristor has a first gate electrode contacting the p-type base layer and a second gate electrode formed on a channel region of the p-type base layer through a gate insulating film. An n+-type layer of the n-type emitter layer immediately below a cathode electrode and an n--type layer of the n-type emitter layer contacting the channel region are formed in different manufacturing steps, and an emitter breakdown voltage and the threshold voltage of the second gate electrode are optimally set.

摘要翻译： 根据本发明，公开了一种包括p型结构的绝缘栅GTO晶闸管，其包括p型发射极层，n型基极层，p型基极层和n型发射极层。 晶闸管具有通过栅极绝缘膜与p型基极层接触的第一栅电极和形成在p型基极层的沟道区上的第二栅电极。 在不同的制造步骤中形成正好在阴极电极正下方的n型发射极层的n +型层和与沟道区接触的n型发射极层的n型层，并且发射极击穿电压和阈值 最优地设定第二栅电极的电压。