公开(公告)号：US07785999B2

公开(公告)日：2010-08-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/44 ,  H01L21/8242

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US20090212369A1

公开(公告)日：2009-08-27

申请号：US12037158

申请日：2008-02-26

申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

公开(公告)号：US20080272437A1

公开(公告)日：2008-11-06

申请号：US11743101

申请日：2007-05-01

申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L27/092 ,  H01L21/3205

CPC分类号： H01L21/823864 ,  H01L21/28176 ,  H01L27/092 ,  H01L29/6656 ,  Y10S438/981

摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

摘要翻译： 公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。 该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。

公开(公告)号：US07271455B2

公开(公告)日：2007-09-18

申请号：US10890753

申请日：2004-07-14

申请人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

发明人： Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam G. Shahidi ,  Michelle L. Steen ,  Clement H. Wann

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20060289903A1

公开(公告)日：2006-12-28

申请号：US11513101

申请日：2006-08-30

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L31/112 ,  H01L29/80

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解， 或更大。

公开(公告)号：US20060138603A1

公开(公告)日：2006-06-29

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L23/58

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US20050280105A1

公开(公告)日：2005-12-22

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低， 或更大。

公开(公告)号：US08415677B2

公开(公告)日：2013-04-09

申请号：US12690178

申请日：2010-01-20

申请人： Praneet Adusumilli ,  Alessandro Callegari ,  Josephine B. Chang ,  Changhwan Choi ,  Martin Michael Frank ,  Michael A. Guillorn ,  Vijay Narayanan

发明人： Praneet Adusumilli ,  Alessandro Callegari ,  Josephine B. Chang ,  Changhwan Choi ,  Martin Michael Frank ,  Michael A. Guillorn ,  Vijay Narayanan

IPC分类号： H01L29/04

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513

摘要： A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

摘要翻译： 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。 在另一个实施例中，在氧阻隔层上存在低电阻率金属层。

公开(公告)号：US20110175147A1

公开(公告)日：2011-07-21

申请号：US12690178

申请日：2010-01-20

申请人： Praneet Adusumilli ,  Alessandro Callegari ,  Josephine B. Chang ,  Changhwan Choi ,  Martin M. Frank ,  Michael A. Guillorn ,  Vijay Narayanan

发明人： Praneet Adusumilli ,  Alessandro Callegari ,  Josephine B. Chang ,  Changhwan Choi ,  Martin M. Frank ,  Michael A. Guillorn ,  Vijay Narayanan

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513

摘要： A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

摘要翻译： 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。 在另一个实施例中，在氧阻隔层上存在低电阻率金属层。