Method and system for a GAN vertical JFET with self-aligned source metallization
    41.
    发明授权
    Method and system for a GAN vertical JFET with self-aligned source metallization 有权
    具有自对准源金属化的GAN垂直JFET的方法和系统

    公开(公告)号:US08841708B2

    公开(公告)日:2014-09-23

    申请号:US13468332

    申请日:2012-05-10

    IPC分类号: H01L29/808

    摘要: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

    摘要翻译: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。 沟道结构包括第一III族氮化物外延材料,其特征在于一个或多个沟道侧壁。 半导体器件还包括耦合到沟道结构的源极区域。 源区包括第二III族氮化物外延材料。 所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构,与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。 电介质层的顶表面与源区的顶表面基本上共面。

    Vertical GaN JFET with gate source electrodes on regrown gate
    42.
    发明授权
    Vertical GaN JFET with gate source electrodes on regrown gate 有权
    在再生栅上具有栅极源电极的垂直GaN JFET

    公开(公告)号:US08698164B2

    公开(公告)日:2014-04-15

    申请号:US13315720

    申请日:2011-12-09

    IPC分类号: H01L29/808 H01L21/335

    摘要: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

    摘要翻译: 半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 第一电极电耦合到GaN衬底的第二表面。 半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。 第一GaN外延层包括沟道区。 第二GaN外延层包括栅极区域和边缘端接结构。 耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

    Epitaxial Lift-Off and Wafer Reuse
    47.
    发明申请
    Epitaxial Lift-Off and Wafer Reuse 审中-公开
    外延提升和晶圆再利用

    公开(公告)号:US20120309172A1

    公开(公告)日:2012-12-06

    申请号:US13118900

    申请日:2011-05-31

    IPC分类号: H01L21/20

    摘要: A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.

    摘要翻译: 根据本发明的实施例的重新使用III族氮化物生长衬底的方法包括在III族氮化物衬底上外延生长III族氮化物半导体结构。 III族氮化物半导体结构包括在牺牲层上生长的牺牲层和附加层。 牺牲层植入至少一种植入物种。 在注入的牺牲层处将III族氮化物衬底与附加层分离。 在一些实施例中,III族氮化物衬底是GaN,牺牲层是GaN,含铝的III族氮化物层或含铟的III族氮化物层。 在一些实施例中,通过蚀刻注入的牺牲层将III族氮化物衬底与附加层分离。

    Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back
    49.
    发明授权
    Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back 有权
    通过再生长和回蚀刻制造氮化镓合并的P-i-N肖特基(MPS)二极管的方法

    公开(公告)号:US08969994B2

    公开(公告)日:2015-03-03

    申请号:US13585121

    申请日:2012-08-14

    摘要: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.

    摘要翻译: MPS二极管包括以第一导电类型和第一掺杂剂浓度为特征的III族氮化物衬底,其具有第一侧和第二侧。 MPS二极管还包括III族氮化物外延结构,其包括耦合到衬底的第一侧的第一III族氮化物外延层,其中第一III族氮化物外延层的区域包括突起阵列。 III族氮化物外延结构还包括多个第二导电类型的III族氮化物区域,每个部分设置在相邻的突起之间。 第二导电类型的多个III族氮化物区域中的每一个包括横向位于相邻突起之间的第一部分和沿着垂直于衬底的第一侧的方向延伸的第二部分。 MPS二极管还包括电耦合到一个或多个突起和一个或多个第二部分的第一金属结构。

    Method of fabricating a GaN P-i-N diode using implantation
    50.
    发明授权
    Method of fabricating a GaN P-i-N diode using implantation 有权
    使用注入制造GaN P-i-N二极管的方法

    公开(公告)号:US08822311B2

    公开(公告)日:2014-09-02

    申请号:US13335329

    申请日:2011-12-22

    IPC分类号: H01L29/20 H01L29/24

    摘要: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

    摘要翻译: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。