公开(公告)号：US10199011B2

公开(公告)日：2019-02-05

申请号：US14023420

申请日：2013-09-10

Applicant: APPLE INC.

Inventor： Ulrich T. Barnhoefer ,  Robert E. Jeter

IPC: G09G3/36 ,  G09G5/10 ,  G09G3/34

Abstract: Systems, methods, and devices are provided for generating a tone mapping function used in adjusting the power consumed by a backlight of an electronic display. One such method includes sampling an image frame in framebuffer space and generating a tone mapping function in linear space. The tone mapping function may have at least two portions: a nondistorting portion that does not to distort pixels to which it applies when an intensity of a backlight of the electronic display is modified and a distorting portion that does distort pixels to which it applies when the intensity of the backlight is modified. Thereafter, the intensity of the backlight may be modified based at least in part on the nondistorting portion of the tone mapping function, the tone mapping function converted to framebuffer space, and the tone mapping function applied to the image frame or a subsequent image frame.

公开(公告)号：US09990973B1

公开(公告)日：2018-06-05

申请号：US15436212

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Fabien S. Faure

IPC: G11C7/22

CPC classification number: G06F13/42 ,  G11C2207/2254

Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.

公开(公告)号：US20180032281A1

公开(公告)日：2018-02-01

申请号：US15225343

申请日：2016-08-01

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

公开(公告)号：US09698797B1

公开(公告)日：2017-07-04

申请号：US15210852

申请日：2016-07-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Suhas Kumar Suvarna Ramesh ,  Venkata Ramana Malladi ,  Thomas H. Huang ,  Rakesh L. Notani ,  Robert E. Jeter ,  Kai Lun Hsiung

IPC: H03L7/00 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/23

Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

公开(公告)号：US09666264B1

公开(公告)日：2017-05-30

申请号：US15187886

申请日：2016-06-21

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Xingchao C. Yuan

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A method and apparatus for memory calibration averaging is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller. The memory controller includes a calibration control circuit that periodically performs calibrations of the memory subsystem. Calibration may be performed for a delay applied to a data strobe used to synchronized transfers of data between the memory controller and the memory, and a reference voltage used to distinguish between a logic 0 and a logic 1 during memory reads. Following the performance of a calibration, the values of the delay and the reference voltage may be set based on an average of a most recent number of calibrations.

公开(公告)号：US09640244B1

公开(公告)日：2017-05-02

申请号：US15083786

申请日：2016-03-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani

IPC: G11C29/04 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50004 ,  G11C29/50008 ,  G11C29/50012 ,  G11C2029/1208 ,  G11C2029/5002 ,  G11C2207/2254

Abstract: A method and apparatus for pre-calibration of various system performance states is disclosed. In one embodiment, a method includes, for each of a number of different performance states (or operating points), performing initial calibrations of various parameters associated with transfers of data between a memory and a memory controller. After completing the initial calibrations, the calibrated values are stored. Thereafter, during normal operation and following a change to a new performance state, the values of the various parameters are set to the values to which they were calibrated during the initial calibration for that state.

公开(公告)号：US20240211151A1

公开(公告)日：2024-06-27

申请号：US18596046

申请日：2024-03-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  David A. Knopf ,  Satish B. Dulam ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan

IPC: G06F3/06 ,  G11C7/22

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/22 ,  G11C2207/2254

Abstract: An apparatus for performing a write data strobe concurrent with a reference voltage calibration is disclosed. A memory controller circuit is configured to convey a write clock signal to a memory. The memory controller circuit includes a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory. The memory controller further includes a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value. The calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.

公开(公告)号：US11875871B2

公开(公告)日：2024-01-16

申请号：US18054056

申请日：2022-11-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

CPC classification number: G11C5/148 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G11C5/141 ,  G11C2207/2254

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US20230115215A1

公开(公告)日：2023-04-13

申请号：US18054056

申请日：2022-11-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US11527269B2

公开(公告)日：2022-12-13

申请号：US16716616

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.