公开(公告)号：US20110001565A1

公开(公告)日：2011-01-06

申请号：US12849561

申请日：2010-08-03

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H03F3/16 ,  H03F1/22

CPC分类号： H03F1/086 ,  H03F3/3001 ,  H03F3/45179 ,  H03F2200/153 ,  H03F2203/30033 ,  H03F2203/45028 ,  H03F2203/45318 ,  H03F2203/45424

摘要： A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal.

摘要翻译： 多级AB类放大器系统包括第一AB类放大器电路和第二AB类放大器电路。 电流镜电路与第一AB类放大器电路连接。 偏置电路与电流镜电路连通。 频率补偿电路设置在偏置电路和第二AB类放大器电路之间。 共模反馈电路与第二AB类放大器电路进行通信。 共模反馈电路被配置为产生反馈信号。

公开(公告)号：US07863657B2

公开(公告)日：2011-01-04

申请号：US11586470

申请日：2006-10-25

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H01L29/72

CPC分类号： H01L29/0692 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7816

摘要： An integrated circuit comprises a first drain region having a symmetric shape across at least one of horizontal and vertical centerlines. A first gate region has a first shape that surrounds the first drain region. A second drain region has the symmetric shape. A second gate region has the first shape that surrounds the second drain region. A connecting gate region connects the first and second gate regions. A first source region is arranged adjacent to and on one side of the first gate region, the second gate region and the connecting gate region. A second source region is arranged adjacent to and on one side of side of the first gate region, the second gate region and the connecting gate region.

摘要翻译： 集成电路包括在水平和垂直中心线中的至少一个上具有对称形状的第一漏极区域。 第一栅极区域具有围绕第一漏极区域的第一形状。 第二漏区具有对称形状。 第二栅极区域具有围绕第二漏极区域的第一形状。 连接栅极区域连接第一和第二栅极区域。 第一源极区域布置成与第一栅极区域，第二栅极区域和连接栅极区域相邻并且在其一侧。 第二源极区域布置成与第一栅极区域，第二栅极区域和连接栅极区域的侧面相邻并且在一侧上。

公开(公告)号：US07835097B1

公开(公告)日：2010-11-16

申请号：US11242371

申请日：2005-10-03

申请人： Farbod Aram ,  Sehat Sutardja

发明人： Farbod Aram ,  Sehat Sutardja

IPC分类号： G11B5/09

CPC分类号： H03F3/183 ,  G11B5/09 ,  G11B2005/0013

摘要： A magnetic storage circuit comprises a preamplifier writer that selectively generates a write current that has a boost stage and a settling stage. An impedance changing circuit communicates with the preamplifier writer and provides a lower resistance value during the boost stage and a higher resistance value during the settling stage.

摘要翻译： 磁存储电路包括一个前置放大器写入器，其选择性地产生具有升压级和稳定级的写入电流。 阻抗改变电路与前置放大器写入器通信，并且在升压阶段期间提供较低的电阻值，在稳定阶段期间提供较高的电阻值。

公开(公告)号：US20100259908A1

公开(公告)日：2010-10-14

申请号：US12731782

申请日：2010-03-25

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H05K7/00 ,  H01L23/495

CPC分类号： H01L21/50 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged semiconductor is disclosed. The packaged semiconductor comprises a conductive integral frame that includes an inner portion and a ring portion encircling the inner portion, a semiconductor die that is mounted to a first surface of the inner portion of the conductive frame, and a casing that supports the conductive frame and covers the semiconductor die. Sections of the conductive frame that connect the inner portion to the ring portion are removed after the casing is applied to the conductive frame.

摘要翻译： 公开了一种封装半导体。 封装半导体包括导电整体框架，其包括内部部分和环绕内部部分的环形部分，安装到导电框架的内部部分的第一表面的半导体管芯和支撑导电框架的壳体， 覆盖半导体芯片。 在将壳体施加到导电框架之后，将内部部分连接到环部分的导电框架的部分被去除。

公开(公告)号：US07804904B1

公开(公告)日：2010-09-28

申请号：US11089010

申请日：2005-03-24

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H03M1/0626 ,  H03M1/66 ,  H04L25/028

摘要： A communication circuit includes a near end transmitter, a hybrid having an input in communication with an output of the near end transmitter, and a near end adjustable load replication transmitter having an adjustable load. The communication circuit further includes a subtractor configured to subtract an output from the near end adjustable load replication transmitter from the output from the near end transmitter and the hybrid. The communication circuit further includes a near end receiver responsive to an output of the subtractor and a calibration circuit configured to adjust the adjustable load against a reference load.

摘要翻译： 通信电路包括近端发射机，具有与近端发射机的输出通信的输入的混合器以及具有可调载荷的近端可调载荷复制发射机。 通信电路还包括减法器，其被配置为从近端可变负载复制发射机的输出中减去来自近端发射机和混合的输出。 通信电路还包括响应于减法器的输出的近端接收器和被配置为相对于参考负载调节可调节负载的校准电路。

公开(公告)号：US07796952B1

公开(公告)日：2010-09-14

申请号：US10701626

申请日：2003-11-06

申请人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse

发明人： Xiaodong Jin ,  Sehat Sutardja ,  Lawrence Tse

IPC分类号： H04B1/38

CPC分类号： H04B1/0064 ,  H04B7/0805

摘要： A system for communicating information signals includes a receiver in selective communication with a first antenna and a second antenna. The receiver is configured to selectively receive information signals via the first or second antenna. The system includes a first low-noise amplifier in communication with the first antenna and in selective communication with the receiver. The first low-noise amplifier is configured to amplify a first information signal received by the first antenna to generate a first amplified signal. The system includes a second low-noise amplifier in communication with the second antenna and in selective communication with the receiver. At least the first and second low-noise amplifiers are formed on a monolithic substrate. The second low-noise amplifier is configured to amplify a second information signal received by the second antenna to generate a second amplified signal. Either the first or second amplified signal is selectively applied to the receiver.

摘要翻译： 用于传送信息信号的系统包括与第一天线和第二天线选择性通信的接收机。 接收器被配置为经由第一或第二天线选择性地接收信息信号。 该系统包括与第一天线通信并与接收机选择性通信的第一低噪声放大器。 第一低噪声放大器被配置为放大由第一天线接收的第一信息信号以产生第一放大信号。 该系统包括与第二天线通信并与接收机选择性通信的第二低噪声放大器。 至少第一和第二低噪声放大器形成在单片基板上。 第二低噪声放大器被配置为放大由第二天线接收的第二信息信号以产生第二放大信号。 第一或第二放大信号被选择性地施加到接收器。

公开(公告)号：US07788514B2

公开(公告)日：2010-08-31

申请号：US12152030

申请日：2008-05-12

申请人： Sehat Sutardja ,  Hong-Yi Chen

发明人： Sehat Sutardja ,  Hong-Yi Chen

IPC分类号： G06F1/32

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0897 ,  G06F13/28 ,  G06F2212/222 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode.

公开(公告)号：US07787324B2

公开(公告)日：2010-08-31

申请号：US11870833

申请日：2007-10-11

申请人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

发明人： Sehat Sutardja ,  Jason T. Su ,  Hong-Yi Chen ,  Jason Sheu ,  Jensen Tjeng

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G06F12/0877 ,  G06F12/0882 ,  G06F12/0893 ,  G06F2212/1028 ,  G11C7/1027 ,  G11C7/12 ,  G11C11/418 ,  G11C2207/104 ,  G11C2207/2245 ,  Y02D10/13

摘要： A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.

摘要翻译： 处理器包括高速缓冲存储器。 高速缓冲存储器包括单元阵列，字线和位线。 控制模块使得字线的字线能够访问所启用的字线中的第一单元。 控制模块禁用字线并将字线保持在禁用状态，以访问字线中的第二个单元格。

公开(公告)号：US07760525B2

公开(公告)日：2010-07-20

申请号：US10693787

申请日：2003-10-24

申请人： Sehat Sutardja

发明人： Sehat Sutardja

IPC分类号： H02M7/48

CPC分类号： H02M3/1584 ,  H02M3/157 ,  H02M2001/0012

摘要： A regulator for converting energy from an input source to a voltage of an output. The regulator comprising at least two conduction switches to conduct energy from the input source to the output. Each of the conduction switches operated at approximately 50% duty cycle. At least two inductors in communication with the at least two conduction switches, the at least two inductors wound together on a common core and each inductor having a polarity such that DC currents in the inductors cancel each other. The inductors having a coefficient of coupling approximately greater than 0.99. At least two freewheeling switches in communication with the at least two conduction switches to provide a path for current during non-conduction periods. A drive signal generator to generate drive signals for controlling the at least two conduction switches.

摘要翻译： 用于将能量从输入源转换成输出电压的调节器。 调节器包括至少两个导通开关，以将能量从输入源传导到输出端。 每个导通开关以大约50％的占空比工作。 与所述至少两个导通开关连通的至少两个电感器，所述至少两个电感器在公共芯体上缠绕在一起，并且每个电感器具有使得所述电感器中的直流电流相互抵消的极性。 电感器的耦合系数近似大于0.99。 至少两个续流开关与至少两个导通开关连通，以在非导通时段期间为电流提供路径。 驱动信号发生器，用于产生用于控制所述至少两个导通开关的驱动信号。

公开(公告)号：US07737788B1

公开(公告)日：2010-06-15

申请号：US12004261

申请日：2007-12-20

申请人： Pierte Roo ,  Sehat Sutardja

发明人： Pierte Roo ,  Sehat Sutardja

IPC分类号： H03F3/04

CPC分类号： H03F3/265 ,  H03F1/22

摘要： A communication device includes a first polarity driver circuit including a first current source, a first amplifier that receives an input signal, that controls the first current source, and that receives a signal from the first current source, a first cascode device arranged in a cascode configuration with the first current source, and a second amplifier that receives a bias signal, that controls the first cascode device, and that receives a signal from the first cascode device.

摘要翻译： 通信装置包括第一极性驱动器电路，其包括第一电流源，接收输入信号的第一放大器，其控制第一电流源，并且接收来自第一电流源的信号;布置在共源共栅中的第一共源共栅器件 配置有第一电流源，以及第二放大器，其接收控制第一共源共用器件并从第一共源共栅器件接收信号的偏置信号。