公开(公告)号：US06660638B1

公开(公告)日：2003-12-09

申请号：US10038389

申请日：2002-01-03

申请人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

发明人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

IPC分类号： H01L21461

CPC分类号： C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

摘要翻译： 当前执行的CMP中看到的两个问题是浆料颗粒保留在表面上并形成最后一层氧化物的倾向。 这些问题已经通过向浆料中加入一定量的TMAH或TBAH来解决。 这具有使表面被抛光的疏水性的效果。 在该状态下，在CMP结束时，残留的氧化层不会残留在表面上。 许多浆料磨料颗粒也不会保持粘附到新鲜抛光的表面。 那些可以通过简单的冲洗或抛光容易地去除。 作为替代方案，CMP工艺可以分三个阶段执行 - 第一个惯例CMP，然后在TMAH或TBAH的溶液中抛光，最后进行柔和的冲洗或抛光。

公开(公告)号：US09893163B2

公开(公告)日：2018-02-13

申请号：US13289038

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/94 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

摘要： A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

公开(公告)号：US08946829B2

公开(公告)日：2015-02-03

申请号：US13273527

申请日：2011-10-14

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang ,  Chi-Wen Liu

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/66818 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/7854

摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.

摘要翻译： 半导体装置包括具有成形翅片和规则翅片的鳍状场效应晶体管（FinFET）。 成形翅片的顶部可以比普通翅片的顶部更小，更大，更薄或更短。 成形翅片和规则翅片的底部是相同的。 FinFET可以仅具有一个或多个成形翅片，一个或多个规则翅片，或者成形翅片和规则翅片的混合物。 形成一个鳍片的半导体制造工艺包括形成一个鳍片的光刻开口，可选地掺杂鳍片的一部分，以及蚀刻鳍片的一部分。

公开(公告)号：US20130113072A1

公开(公告)日：2013-05-09

申请号：US13289038

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

摘要： A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

摘要翻译： 公开了用于制造3D电容器的3D电容器和方法。 示例性3D电容器包括包括鳍结构的衬底，鳍结构包括多个翅片。 3D电容器还包括设置在基板上并且在多个翅片中的每一个之间的绝缘材料。 3D电容器还包括设置在多个鳍片中的每一个上的电介质层。 3D电容器还包括设置在翅片结构的第一部分上的第一电极。 第一电极与翅片结构的表面直接接触。 3D电容器还包括设置在鳍结构的第二部分上的第二电极。 第二电极直接设置在电介质层上，翅片结构的第一和第二部分是不同的。

公开(公告)号：US20130082304A1

公开(公告)日：2013-04-04

申请号：US13252892

申请日：2011-10-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括：衬底，其包括设置在衬底上的鳍结构。 翅片结构包括一个或多个翅片。 半导体器件还包括设置在基板上的绝缘材料。 半导体器件还包括设置在鳍结构的一部分上和绝缘材料的一部分上的栅极结构。 栅极结构横穿翅片结构的每个翅片。 半导体器件还包括由具有连续且不间断表面积的材料形成的源极和漏极特征。 源极和漏极特征包括在与绝缘材料的平行平面中的表面直接接触的平面中的表面，翅片结构的一个或多个翅片中的每一个以及栅极结构。

公开(公告)号：USD639139S1

公开(公告)日：2011-06-07

申请号：US29307442

申请日：2008-04-21

申请人： Michael O. Misner ,  Chi-Wen Liu

设计人： Michael O. Misner ,  Chi-Wen Liu

公开(公告)号：US07795534B2

公开(公告)日：2010-09-14

申请号：US11984477

申请日：2007-11-19

申请人： Chin-Lai Lin ,  Chih-Ming Fan ,  Chi-Wen Liu

发明人： Chin-Lai Lin ,  Chih-Ming Fan ,  Chi-Wen Liu

IPC分类号： H02G3/14

CPC分类号： G06F1/181

摘要： A sliding cover faceplate and an electronic device using the same are provided. The sliding cover faceplate includes a sliding cover, a cover plate, and a sliding structure. The cover plate is provided on the electronic device, and the sliding cover is disposed on one side of the cover plate. The sliding structure includes a guiding portion and an elastic positioning portion. The guiding portion is disposed on the cover plate and is connected to the sliding cover to guide the sliding cover to slide between a first location and a second location on the cover plate. The elastic positioning portion connects the cover plate with the sliding cover to provide an elastic force to the sliding cover, such that when the sliding cover slides close to the first location or the second location, the sliding cover is automatically positioned on the first location or the second location.

摘要翻译： 提供一种滑盖面板和使用其的电子装置。 滑盖面板包括滑盖，盖板和滑动结构。 盖板设置在电子设备上，滑盖位于盖板的一侧。 滑动结构包括引导部分和弹性定位部分。 引导部分设置在盖板上并连接到滑盖上，以引导滑盖在盖板上的第一位置和第二位置之间滑动。 弹性定位部分将盖板与滑动盖连接，以向滑动盖提供弹性力，使得当滑动盖滑动靠近第一位置或第二位置时，滑动盖自动定位在第一位置或 第二个位置。

公开(公告)号：US07432192B2

公开(公告)日：2008-10-07

申请号：US11347946

申请日：2006-02-06

申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

公开(公告)号：US07256120B2

公开(公告)日：2007-08-14

申请号：US11024917

申请日：2004-12-28

申请人： Jung-Chin Tsao ,  Chi-Wen Liu ,  Hsien-Ping Feng ,  Hsi-Kuei Cheng ,  Steven Lin ,  Min-Yuan Cheng

发明人： Jung-Chin Tsao ,  Chi-Wen Liu ,  Hsien-Ping Feng ,  Hsi-Kuei Cheng ,  Steven Lin ,  Min-Yuan Cheng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/02068 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76876

摘要： A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.

摘要翻译： 一种形成具有减少的缺陷的金属层的方法，包括提供其上形成有电介质层的结构，形成具有开口的电介质层，用金属种子层衬套开口，用清洁工艺处理金属种子层以除去 从其中污染，并在金属种子层上形成金属层。

公开(公告)号：US07252750B2

公开(公告)日：2007-08-07

申请号：US10664347

申请日：2003-09-16

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

IPC分类号： C25D17/00

CPC分类号： C25D5/48 ,  C25D5/028 ,  Y10S204/07

摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

摘要翻译： 用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。 双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。 外部电压环连接到正电压源，内部电压环连接到负电压源。 内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。 通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。