公开(公告)号：USD639139S1

公开(公告)日：2011-06-07

申请号：US29307442

申请日：2008-04-21

申请人： Michael O. Misner ,  Chi-Wen Liu

设计人： Michael O. Misner ,  Chi-Wen Liu

公开(公告)号：US09287385B2

公开(公告)日：2016-03-15

申请号：US13223682

申请日：2011-09-01

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795

摘要： A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

摘要翻译： 多翅片装置包括基板和形成在基板上的多个翅片。 源极和漏极区域形成在相应的鳍片中。 在基板上形成电介质层。 电介质层具有与第一鳍片的一侧相邻的第一厚度，并且具有与第一厚度不同的第二厚度，邻近鳍片的相对侧。 连续的栅极结构被形成为覆盖多个翅片，连续栅极结构邻近每个翅片的顶表面和至少一个翅片的至少一个侧壁表面。 通过调整电介质层的厚度，所得到的器件的通道宽度可以被微调。

公开(公告)号：US08723236B2

公开(公告)日：2014-05-13

申请号：US13272305

申请日：2011-10-13

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/76224 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/785

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.

公开(公告)号：US07221584B2

公开(公告)日：2007-05-22

申请号：US11053379

申请日：2005-02-08

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny D. Tang

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny D. Tang

IPC分类号： G11C11/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/228

摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.

摘要翻译： 磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。 第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

公开(公告)号：US20060216930A1

公开(公告)日：2006-09-28

申请号：US11347946

申请日：2006-02-06

申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

公开(公告)号：US07071100B2

公开(公告)日：2006-07-04

申请号：US10788912

申请日：2004-02-27

申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

公开(公告)号：US20060043463A1

公开(公告)日：2006-03-02

申请号：US10932198

申请日：2004-09-01

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Wen-Tin Chu

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Wen-Tin Chu

IPC分类号： H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device includes a source and a drain formed in a substrate, a tunneling dielectric formed on the substrate between the source and the drain, and a floating gate disposed over the tunneling dielectric having a band-gap energy less than the energy band-gap of silicon.

摘要翻译： 半导体器件包括形成在衬底中的源极和漏极，形成在源极和漏极之间的衬底上的隧道电介质，以及设置在隧道电介质上的浮置栅极，其带隙能量小于能带隙能量 的硅。

公开(公告)号：US20060033133A1

公开(公告)日：2006-02-16

申请号：US11053379

申请日：2005-02-08

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny Tang

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny Tang

IPC分类号： H01L29/94

CPC分类号： H01L27/228

摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.

摘要翻译： 磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。 第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

公开(公告)号：US06979656B2

公开(公告)日：2005-12-27

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

摘要翻译： 制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。 当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。 具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。 包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

公开(公告)号：US20050245064A1

公开(公告)日：2005-11-03

申请号：US10835315

申请日：2004-04-28

申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/687 ,  H01L21/768

CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。