公开(公告)号：US20050105353A1

公开(公告)日：2005-05-19

申请号：US10954642

申请日：2004-09-30

申请人： Stefan Trost ,  Georg Tempel ,  Matthias Ernst ,  Martin Steinbruck

发明人： Stefan Trost ,  Georg Tempel ,  Matthias Ernst ,  Martin Steinbruck

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/3427

摘要： Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

摘要翻译： 在对存储单元阵列的选定闪存单元进行重新编程之前，通过Fowler-Nordheim隧道从电子区域（C）中的存储层（M）中移除的电子，用于存储器单元的初始编程的较低电位是 而相关联的位线（BL _{m ）保持在基本电位的情况下被施加到相关字线（WL SUB）。 由此实现的是在编程操作期间发生的门扰动不会导致沿着受影响的字线（WL SUB）的不稳定的位。}

公开(公告)号：US06787843B2

公开(公告)日：2004-09-07

申请号：US10462514

申请日：2003-06-16

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active regions are formed with a first insulating layer situated above them, a charge-storing layer, a second insulating layer and a control layer. In order to realize a particularly small cell area, in a third insulating layer situated thereabove, openings are formed above at least partial regions of source/drain regions, which are each directly contact-connected via the openings by source and drain lines formed on an insulating web.

摘要翻译： 非易失性半导体存储单元，相关半导体电路结构以及制造方法，其中在衬底中形成有位于其上的第一绝缘层的有源区，电荷存储层，第二绝缘层和控制层 层。 为了实现特别小的单元区域，在位于其上的第三绝缘层中，在源极/漏极区域的至少部分区域之上形成开口，所述至少部分区域通过形成在其上的源极和漏极线路经由开口直接接触连接 绝缘网。

公开(公告)号：US06531359B1

公开(公告)日：2003-03-11

申请号：US09596420

申请日：2000-06-19

申请人： Georg Tempel ,  Christoph Kutter

发明人： Georg Tempel ,  Christoph Kutter

IPC分类号： H01L21336

CPC分类号： H01L27/11517

摘要： A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in accordance with an STI (Shallow Trench Isolation) technique, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD depositing an oxide or nitride laterally onto the hard mask and onto the side wall oxides to define a spacer. Spacer channels are etched into the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied to mask each two adjacent coated word lines on mutually facing sections, including the spacer channel located between these word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked on mutually facing sections. The SAS resist mask is exposed. Those regions of the insulation zones which are not covered by the SAS perforated mask are anisotropic etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the uncovered silicon substrate. The SAS perforated mask is removed to uncover a resultant structure.

摘要翻译： 一种用于制造存储单元阵列，特别是EPROM或EEPROM存储单元阵列的方法，包括根据STI（浅沟槽隔离）技术在硅衬底上埋设绝缘区，在绝缘区上形成字线，覆盖字 具有硬掩模和侧壁氧化物的线和CVD将氧化物或氮化物横向沉积到硬掩模上并到侧壁氧化物上以限定间隔物。 间隔通道被蚀刻到相邻字线之间的绝缘区域中。 应用SAS（自对准源）抗蚀剂掩模来掩蔽相互面对的部分上的每两个相邻涂覆的字线，包括位于这些字线之间的间隔通道，而掩蔽的字线对的每两个相邻的被掩蔽的字线保持相互掩蔽 面向部分。 SAS抗蚀剂掩模露出。 未被SAS穿孔掩模覆盖的绝缘区域的那些区域是各向异性蚀刻的，未覆盖的间隔物通道的底部至少下降至未覆盖的硅衬底的表面。 移除SAS穿孔的面罩以露出所得到的结构。

公开(公告)号：US08691660B2

公开(公告)日：2014-04-08

申请号：US12883023

申请日：2010-09-15

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/763

CPC分类号： H01L21/763 ,  H01L21/76229 ,  H01L21/76232

摘要： The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

摘要翻译： 本发明涉及具有沟槽隔离和相关制造方法的半导体部件，具有具有覆盖绝缘层（10,11）的深隔离沟槽的沟槽隔离（STI，TTI），侧壁绝缘层（6）和 导电填充层（7），其在沟槽的底部区域电连接到半导体衬底的预定掺杂区域（1）。 使用与侧壁绝缘层（6）和导电填充层（7）具有深接触沟槽的沟槽接触（DTC），其同样电连接到 半导体衬底在接触沟槽的底部区域中，使得可以以减小的面积要求来改善电屏蔽性能。

公开(公告)号：US08198681B2

公开(公告)日：2012-06-12

申请号：US12606876

申请日：2009-10-27

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/28194 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/28167 ,  H01L21/314 ,  H01L21/3144 ,  H01L21/316 ,  H01L21/7624 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66772 ,  H01L29/6678 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78657

摘要： The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

摘要翻译： 本发明涉及一种具有应力吸收半导体层（SA）和相关制造方法的半导体元件，用于在载体材料（1）上形成机械应力的结晶应力发生器层（SG）。 在应力发生器层（SG）的表面形成有将产生的应力吸收半导体层（SA）的机械应力透过的绝缘应力传递层（2），除了 还获得了改善的载流子迁移率，改善了半导体组件的电性能。

公开(公告)号：US08154090B2

公开(公告)日：2012-04-10

申请号：US12079003

申请日：2008-03-24

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S438/954

摘要： The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

摘要翻译： 本发明涉及一种非易失性半导体存储单元及其相关的制造方法，源区域（7），漏极区域（8）和位于衬底（1）之间的沟道区域之间。 为了实现局部定界的存储位置（LB，RB），位于第一绝缘层（2）上的非导电电荷存储层（3）被中断（U）划分，从而特别地防止 记忆位置（LB，RB）之间的横向电荷传输并显着改善电荷保持性质。

公开(公告)号：US20110003457A1

公开(公告)日：2011-01-06

申请号：US12883023

申请日：2010-09-15

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/762

CPC分类号： H01L21/763 ,  H01L21/76229 ,  H01L21/76232

摘要： The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

摘要翻译： 本发明涉及具有沟槽隔离和相关制造方法的半导体部件，具有具有覆盖绝缘层（10,11）的深隔离沟槽的沟槽隔离（STI，TTI），侧壁绝缘层（6）和 导电填充层（7），其在沟槽的底部区域电连接到半导体衬底的预定掺杂区域（1）。 使用与侧壁绝缘层（6）和导电填充层（7）具有深接触沟槽的沟槽接触（DTC），其同样电连接到 半导体衬底在接触沟槽的底部区域中，使得可以以减小的面积要求来改善电屏蔽性能。

公开(公告)号：US07709836B2

公开(公告)日：2010-05-04

申请号：US10507787

申请日：2003-03-12

申请人： Bernhard Knott ,  Georg Tempel

发明人： Bernhard Knott ,  Georg Tempel

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L29/7923

摘要： The invention relates to a detector arrangement (100), a method for the detection of electrical charge carriers and use of an ONO field effect transistor for detection of an electrical charge. The detector arrangement (100) has an ONO field effect transistor embodied on and/or in a substrate (101), for the detection of electrical charge carriers, such that the electrical charge carrier (103) for detection may be introduced into die ONO field effect transistor layer sequence (102), a recording unit (104), coupled to the ONO field effect transistor, for recording an electrical signal characteristic of the amount and/or the charge carrier type for the electrical charge carrier (103) introduced into the ONO layer sequence (102) and an analytical unit for determining the amount and/or the charge carrier type of the electrical charge carrier (103) introduced into the ONO layer sequence (102) from the characteristic electrical signal.

摘要翻译： 本发明涉及一种检测器装置（100），一种用于检测电荷载流子的方法和用于检测电荷的ONO场效应晶体管的使用。 检测器装置（100）具有体现在基板（101）上和/或基板（101）中的ONO场效应晶体管，用于检测电荷载流子，使得用于检测的电荷载体（103）可以被引入管芯ONO场 效应晶体管层序列（102），耦合到ONO场效应晶体管的记录单元（104），用于记录引入到电荷载体（103）的电荷载体（103）的量和/或电荷载体类型的电信号特征 ONO层序列（102）和用于根据特征电信号确定引入到ONO层序列（102）中的电荷载体（103）的量和/或电荷载体类型的分析单元。

公开(公告)号：US20100084691A1

公开(公告)日：2010-04-08

申请号：US12606876

申请日：2009-10-27

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L29/04

CPC分类号： H01L21/28194 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/28167 ,  H01L21/314 ,  H01L21/3144 ,  H01L21/316 ,  H01L21/7624 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66772 ,  H01L29/6678 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78657

摘要： The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

摘要翻译： 本发明涉及具有应力吸收半导体层（SA）和相关制造方法的半导体部件，用于在载体材料（1）上形成机械应力的结晶应力发生器层（SG）。 在应力发生器层（SG）的表面形成有将产生的应力吸收半导体层（SA）的机械应力透过的绝缘应力传递层（2），除了 还获得了改善的载流子迁移率，改善了半导体组件的电性能。

公开(公告)号：US20100006925A1

公开(公告)日：2010-01-14

申请号：US12561905

申请日：2009-09-17

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L27/115 ,  H01L29/78

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3′) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

摘要翻译： 本发明涉及一种非易失性双晶体管半导体存储单元及相关的制造方法，用于选择晶体管（AT）的源极和漏极区（2）和存储晶体管（ST）形成在衬底（1）中。 存储晶体管（ST）具有第一绝缘层（3），电荷存储层（4），第二绝缘层（5）和存储晶体管控制层（6），而选择晶体管（AT） 绝缘层（3'）和选择晶体管控制层（4 *）。 通过使用不同的材料用于电荷存储层（4）和选择晶体管控制层（4 *），通过使衬底掺杂的电性能保持不变，可以显着提高存储单元的电荷保持性能。