公开(公告)号：US5719445A

公开(公告)日：1998-02-17

申请号：US780053

申请日：1996-12-23

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03H7/30 ,  H03K5/13 ,  H03K19/003 ,  H01L23/34

CPC classification number: H03K19/00323 ,  H03H7/30 ,  H03K5/133 ,  H01L2924/0002

Abstract: Signal propagation times in circuit paths are matched to compensate for signal delays due to differences in the physical parameters, such as lengths, of the circuit paths. This is accomplished by adjusting the length of lead lines and by the addition of resistors in series with shorter lead lines in a chip or die. In a chip with an active device, such as logic, having multiple input lines, the lines are divided into long lines and short lines. All long lines are laid out so as to have the same length and to use the least amount of chip surface area. Similarly, all short lines are laid out on the chip so as to have the same length while using the least amount of chip surface area. With all the short lines having the same propagation time difference relative to all the long lines, the same resistive element is added to all the short lines to effect the same RC delay in signal propagation on the short lines so as to match the signal propagation time on the short lines with that on the long lines.

Abstract translation: 匹配电路路径中的信号传播时间，以补偿由于电路路径的物理参数（例如长度）的差异引起的信号延迟。 这是通过调整引线的长度和通过在芯片或管芯中与较短引线串联的电阻器来实现的。 在具有多个输入线的有源器件（例如逻辑）的芯片中，线被分成长线和短线。 所有长线布置成具有相同的长度并且使用最少量的芯片表面积。 类似地，所有短线布置在芯片上，以便在使用最少量的芯片表面积的同时具有相同的长度。 对于所有短线相对于所有长线具有相同的传播时间差，相同的电阻元件被添加到所有短线，以在短线上的信号传播中产生相同的RC延迟，以便匹配信号传播时间 在短线上与长线上的短线。

公开(公告)号：US5654663A

公开(公告)日：1997-08-05

申请号：US631063

申请日：1996-04-12

Applicant: David C. McClure ,  Thomas A. Teel

Inventor： David C. McClure ,  Thomas A. Teel

IPC: H03K17/14 ,  G05F3/20 ,  H03F1/30 ,  H03F3/16 ,  H03F3/45 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  G05F1/10

CPC classification number: G05F3/205

Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device. The bias circuit may control the slew rate of an output driver, may control the propagation delay through a delay element, and be used to control the duration of a pulse produced by a pulse generating circuit.

Abstract translation: 公开了一种偏置电路，用于产生偏置电压超过电源电压和过程参数的变化。 偏置电路利用分压器基于电源值产生分压。 分压电流被施加到电流镜中的调制晶体管的栅极（偏置为饱和），其控制施加到在线性区域中偏置的线性负载装置的电流。 负载器件两端的电压决定偏置电压。 因此，电源电压的变化被反映在偏置电压中，使得串联晶体管的栅极 - 源极电压在电源电压的变化上是恒定的。 产生不同晶体管电流驱动特性的工艺参数的变化反映在由线性负载装置产生的偏置电压的变化中。 偏置电路可以控制输出驱动器的转换速率，可以通过延迟元件来控制传播延迟，并且用于控制由脉冲发生电路产生的脉冲的持续时间。

公开(公告)号：US5619466A

公开(公告)日：1997-04-08

申请号：US589024

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/419 ,  G11C11/409 ,  C11C7/06

CPC classification number: G11C7/065 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/50 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/2602 ,  G11C2029/5002 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2227 ,  G11C29/06

Abstract: A read circuit for a memory cell includes a sense amplifier and an equilibrate circuit. The sense amplifier is coupled to the memory cell via a pair of data lines, and amplifies the data signals that the memory cell provides. The equilibrate circuit is coupled to the sense amplifier, receives an equilibrate signal, and, when the equilibrate signal has an active level, equilibrates the sense amplifier. When the equilibrate signal has an inactive level, the equilibrate circuit causes the sense amplifier to draw substantially zero supply current, regardless of the levels of any signals on the data lines. The read circuit may also include an enable circuit that receives an enable signal and is coupled to the sense amplifier. When the enable signal has an active level, the enable circuit allows the sense amplifier to amplify the data signals on the data lines. When the enable signal has an inactive level, the enable circuit prohibits the sense amplifier from amplifying the data signals on the data lines.

Abstract translation: 用于存储单元的读取电路包括读出放大器和平衡电路。 读出放大器经由一对数据线耦合到存储单元，并放大存储单元提供的数据信号。 平衡电路耦合到感测放大器，接收平衡信号，并且当平衡信号具有有效电平时，平衡感测放大器。 当平衡信号具有无效电平时，无论数据线上的任何信号的电平如何，均衡电路都会使读出放大器基本上绘制零电源电流。 读取电路还可以包括使能电路，其接收使能信号并耦合到读出放大器。 当使能信号具有有效电平时，使能电路允许读出放大器放大数据线上的数据信号。 当使能信号具有无效电平时，使能电路禁止读出放大器放大数据线上的数据信号。

公开(公告)号：US5589794A

公开(公告)日：1996-12-31

申请号：US360227

申请日：1994-12-20

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G05F1/46 ,  G05F3/26 ,  G05F1/10

CPC classification number: G05F1/465 ,  G05F3/262

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

Abstract translation: 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5579263A

公开(公告)日：1996-11-26

申请号：US362187

申请日：1994-12-22

Applicant: Thomas A. Teel ,  David C. McClure

Inventor： Thomas A. Teel ,  David C. McClure

IPC: G11C7/10 ,  G06F12/00 ,  G06F7/00

CPC classification number: G11C7/1045

Abstract: A memory and a method involving the memory. The memory includes a memory array having a data quantity output for outputting a data quantity and a data output driver having an input for receiving the data quantity and an output for outputting the data quantity from the memory. The memory further includes a data quantity pipeline register having an input for receiving the data quantity and an output coupled to the input of the data output driver. Finally, the memory includes means for selectively coupling a data quantity from the data output of the memory array to the input of the data output driver in a first operational mode and to the input of the data quantity pipeline register in a second operational mode.

Abstract translation: 一种内存和涉及内存的方法。 存储器包括具有用于输出数据量的数据量输出的存储器阵列和具有用于接收数据量的输入的数据输出驱动器和用于从存储器输出数据量的输出。 存储器还包括具有用于接收数据量的输入的数据量流水线寄存器和耦合到数据输出驱动器的输入的输出。 最后，存储器包括用于在第一操作模式中将数据量从存储器阵列的数据输出选择性地耦合到数据输出驱动器的输入的装置，以及在第二操作模式下数据量流水线寄存器的输入的装置。

公开(公告)号：US5557573A

公开(公告)日：1996-09-17

申请号：US484609

申请日：1995-08-21

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/26 ,  G11C29/56 ,  H01L23/58 ,  G11C13/00

CPC classification number: H01L22/32 ,  G01R31/30 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/26 ,  G06F11/2273 ,  H01L2924/3011

Abstract: A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. A test mode control circuit, having a first and a second test mode control input, is used, during special test operation mode, to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the array of memory cells. Contemporaneously are also exercised entire paths of buffers. The integrated circuit is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test one or more integrated circuits on the same wafer in a short time, requiring only a limited number of test signals. It is possible, indeed, to connect in parallel power supply and test inputs of a plurality of integrated circuits and test them simultaneously. For example by connecting only four probes to one of the plurality of integrated circuits (ground, supply voltage and two test mode inputs), it is possible to write all 0's or all 1's and to deselect the entire memory array simultaneously in all integrated circuits during the test. This circuit allows to use very simple test equipment and reduces dramatically test times avoiding consequent burn in of packaged devices.

Abstract translation: 提供了一种电路和相关方法，用于在硅晶片上集成在芯片上的多个存储电路的并行加压。 在特殊测试操作模式期间，使用具有第一测试模式控制输入和第二测试模式控制输入的测试模式控制电路，以将地址缓冲器，数据缓冲器和其它信号缓冲器（如芯片使能或写缓冲器）的输出强制到预定 逻辑值，使得选择所有行和列解码器，并将预定数据写入存储器单元阵列。 同时也行使缓冲区的整个路径。 然后将集成电路加热并在升高的温度下保持所需时间，然后冷却。 以这种方式，可以在短时间内对同一晶片上的一个或多个集成电路进行压力测试，只需要有限数量的测试信号。 实际上，连接多个集成电路的并行电源和测试输入是可能的，同时进行测试。 例如，通过将四个探头连接到多个集成电路（接地，电源电压和两个测试模式输入）中的一个，可以写入所有0或全部1，并在所有集成电路中同时取消选择整个存储器阵列 考试。 该电路允许使用非常简单的测试设备，并大大减少了测试时间，从而避免了包装设备的烧毁。

公开(公告)号：US5551004A

公开(公告)日：1996-08-27

申请号：US69024

申请日：1993-05-28

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  G11C29/00

CPC classification number: G11C29/88 ,  G06F12/0888

Abstract: According to the present invention, faulty isolated bits in the cache memory are made inaccessible to the microprocessor by rendering an appropriate line of data in the cache memory uncacheable to the microprocessor. When faulty data bits are not repairable through conventional repair means such as row/column redundancy, the tag RAM may be programmed with the address of the faulty data bit such that when the microprocessor requests data at that address, a comparator inside the tag RAM generates a signal indicative of a "miss" condition which is an output signal of the tag RAM. The miss condition is communicated to the microprocessor which must access the requested data from main memory. In this way, a cache memory having faulty data bits may still be utilized.

Abstract translation: 根据本发明，高速缓冲存储器中的故障隔离位使微处理器无法访问高速缓冲存储器中适当的数据线，从而对微处理器不可缓解。 当故障数据位不能通过诸如行/列冗余的常规修复手段修复时，标签RAM可以用错误数据位的地址进行编程，使得当微处理器在该地址处请求数据时，标签RAM内的比较器产生 指示作为标签RAM的输出信号的“未命中”状态的信号。 未命中状态被传送到必须从主存储器访问所请求的数据的微处理器。 以这种方式，仍然可以使用具有错误数据位的高速缓冲存储器。

公开(公告)号：US5526317A

公开(公告)日：1996-06-11

申请号：US263048

申请日：1994-06-21

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H01L21/82 ,  G11C29/00 ,  G11C29/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  G11C8/00

CPC classification number: G11C29/76 ,  H01L27/0207

Abstract: Two addresses of an integrated circuit are selected to define a portion of the die which is functional and the portion of the die which will not be used. An input structure for addresses, which may be added to part of the electrostatic discharge (ESD) input structure of a pin, allows an address signal to be set to a predetermined logic level and to not be bonded out to the package. Additionally, another input structure allows the mapping of a signal pin to be changed. The function of a pin may need to be changed to accommodate a pinout for a different density device. This is useful when a die is put into a smaller density device package which has a pin out that does not accommodate the die. In this way, partially functional die that previously were discarded may be utilized, thereby recouping potential losses during manufacturing.

Abstract translation: 选择集成电路的两个地址以限定芯片的功能部分和不使用的芯片部分。 可以添加到引脚的静电放电（ESD）输入结构的一部分的地址的输入结构允许地址信号被设置为预定的逻辑电平并且不被结合到封装。 另外，另一输入结构允许映射要改变的信号引脚。 可能需要改变引脚的功能以适应不同密度器件的引脚排列。 当将管芯放入具有不能容纳管芯的销钉的较小密度的器件封装中时，这是有用的。 以这种方式，可以利用先前被丢弃的部分功能的模具，从而在制造过程中补偿潜在的损失。

公开(公告)号：US5513143A

公开(公告)日：1996-04-30

申请号：US923856

申请日：1992-07-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  G11C7/10 ,  G11C11/419 ,  G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00 ,  G06F12/0893 ,  G11C11/419 ,  G11C7/1078

Abstract: The mechanism for performing writes to the data cache memory in a cache subsystem is modified to reduce the occurrence of microprocessor wait states. Concurrently, with operation of the tag RAM, the write signal from the microprocessor propagates through the data cache up to a point in the internal circuitry of the data cache which is as close as reasonably possible to the memory cell being written. At this point in the circuitry, the write signal is gated by the Match signal from the tag RAM. Address decoding is completed prior to receiving the Match signal, such that when the tag RAM generates a "hit" Match output signal, the write signal is allowed to finish propagating through data cache internal circuitry without additional address set-up time. This allows the memory cell to be written to quickly and reduces the probability of microprocessor wait states. In a preferred embodiment of the present invention, the write signal propagates to a logic function, such as a logic gate, where it is gated by the Match signal from the tag RAM and data. When the tag RAM generates a "hit" Match output signal, the write signal as well as the data is allowed to finish propagating to the memory cell.

Abstract translation: 对缓存子系统中的数据高速缓冲存储器执行写入的机制被修改以减少微处理器等待状态的发生。 同时，随着标签RAM的操作，来自微处理器的写入信号通过数据高速缓存传播到数据高速缓冲存储器的内部电路中的一个点，该数据缓存器的内部电路尽可能接近写入的存储器单元。 在电路的这一点上，写入信号由来自标签RAM的匹配信号选通。 地址解码在接收到匹配信号之前完成，使得当标签RAM产生“命中”匹配输出信号时，允许写入信号通过数据高速缓存内部电路完成传播，而无需额外的地址设置时间。 这允许快速写入存储器单元并降低微处理器等待状态的概率。 在本发明的一个优选实施例中，写入信号传播到诸如逻辑门的逻辑功能，其中它由来自标签RAM和数据的匹配信号选通。 当标签RAM产生“命中”匹配输出信号时，允许写入信号以及数据完成传播到存储器单元。

公开(公告)号：US5487048A

公开(公告)日：1996-01-23

申请号：US41321

申请日：1993-03-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/065

Abstract: A memory system including a memory array having at least two pairs of data lines, first and second data lines, that correspond to columns in the memory array. A first stage is included having inputs connected to the two pairs of data lines. The first stage also has a pair of output lines, a true output lines and a complement output line, wherein output signals generated in the output lines are controlled by a first and second set of transistors. Each transistor in the first set has a gate connected to one of the input lines, and each transistor in the second set is connected in series with one of the transistors in the first set and may be selectively turned on and turned off, wherein of one of the two pairs of data lines may be selected by turning transistors on and off in the second set.

Abstract translation: 一种存储器系统，包括具有对应于存储器阵列中的列的至少两对数据线，第一和第二数据线的存储器阵列。 包括具有连接到两对数据线的输入的第一级。 第一级还具有一对输出线，真实输出线和补码输出线，其中在输出线中产生的输出信号由第一和第二组晶体管控制。 第一组中的每个晶体管具有连接到一个输入线的栅极，并且第二组中的每个晶体管与第一组中的晶体管中的一个串联连接，并且可以选择性地导通和关断，其中一个 可以通过在第二组中打开和关闭晶体管来选择两对数据线。