公开(公告)号：US07053720B2

公开(公告)日：2006-05-30

申请号：US11049163

申请日：2005-02-02

Applicant: Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

Inventor： Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03L7/18

CPC classification number: H03L7/18 ,  H04J3/0685 ,  H04J2203/0082 ,  H04J2203/0089 ,  H04L7/033

Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

公开(公告)号：US07049856B2

公开(公告)日：2006-05-23

申请号：US11031102

申请日：2005-01-06

Applicant: Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

Inventor： Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

IPC: G01R19/00

CPC classification number: H03K5/1532 ,  G01R19/04

Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

公开(公告)号：US07034606B2

公开(公告)日：2006-04-25

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: G06G7/12

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20050271136A1

公开(公告)日：2005-12-08

申请号：US10847829

申请日：2004-05-18

Applicant: David Chung ,  Afshin Momtaz

Inventor： David Chung ,  Afshin Momtaz

IPC: H03H7/30 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract translation: 均衡电路根据一个或多个调整信号的值（例如，均衡系数）调整（例如，均衡）输入信号而不进行乘法运算。 例如，电路可以将系数信号的值加到或减去输入信号的幅度。 这里，系数是否被相加或取决于控制信号的符号。

公开(公告)号：US20050254569A1

公开(公告)日：2005-11-17

申请号：US10846316

申请日：2004-05-14

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03K5/159 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/033 ,  H04L2025/03617

Abstract: A least mean square (“LMS”) circuit generates equalization coefficients using demultiplexed data signals. Serial equalized data output by a decision feedback equalizer is demultiplexed into two or more parallel signals. The LMS clock signal is phase aligned with a retimer clock signal and demultiplexer clock signal to provide data to the LMS circuit in a desired sequence.

Abstract translation: 最小均方（“LMS”）电路使用解复用的数据信号产生均衡系数。 由判决反馈均衡器输出的串行均衡数据被解复用为两个或更多个并行信号。 LMS时钟信号与重新定时器时钟信号和解复用器时钟信号相位对准，以期望的顺序向LMS电路提供数据。

公开(公告)号：US20050135475A1

公开(公告)日：2005-06-23

申请号：US10774724

申请日：2004-02-09

Applicant: Afshin Momtaz ,  Mario Caresosa

Inventor： Afshin Momtaz ,  Mario Caresosa

IPC: H04B10/158 ,  H04B10/18 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04B1/66

CPC classification number: H04B10/66 ,  H04L25/03038 ,  H04L25/03057 ,  H04L2025/0349

Abstract: A communication system having a transmitter transmits an information signal over a communication media and a receiver coupled to the communication media receives the transmitted information signal. The receiver includes a continuous time filter having an adjustable bandwidth for linearly equalizing the transmitted information signal as a function of the adjustable bandwidth. A decision feedback equalizer coupled to the continuous time filter then reduces inter-symbol interference in the filtered information signal.

Abstract translation: 具有发射机的通信系统通过通信介质发送信息信号，并且耦合到通信媒体的接收机接收所发送的信息信号。 接收机包括具有可调节带宽的连续时间滤波器，用于作为可调节带宽的函数线性地均衡所发送的信息信号。 耦合到连续时间滤波器的判决反馈均衡器然后减少滤波信息信号中的符号间干扰。

公开(公告)号：US20050135470A1

公开(公告)日：2005-06-23

申请号：US10774725

申请日：2004-02-09

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03L7/081 ,  H04B10/18 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H03L7/081 ,  H04B10/2507 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349 ,  H04L2025/03579

Abstract: In a method and apparatus for communicating data, a decision feedback equalizer equalizes received data to reduce channel related distortion in the received data. An extracted clock signal is generated from the equalized data. The phase of the extracted clock signal may be adjusted to compensate for processing delay during equalization of the received data. The extracted clock signal may be used to clock a retimer of the decision feedback equalizer to generate recovered data.

Abstract translation: 在用于传送数据的方法和装置中，判决反馈均衡器对接收到的数据进行均衡以减少所接收数据中的信道相关失真。 从均衡数据生成提取的时钟信号。 提取的时钟信号的相位可以被调整以补偿在接收的数据的均衡期间的处理延迟。 提取的时钟信号可以用于对判决反馈均衡器的重定时器进行时钟以产生恢复的数据。

公开(公告)号：US20050128012A1

公开(公告)日：2005-06-16

申请号：US11049163

申请日：2005-02-02

Applicant: Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

Inventor： Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

IPC: H04J3/04 ,  H04J3/06 ,  H04J3/16 ,  H04L7/033 ,  H04Q11/04 ,  H03B1/00

CPC classification number: H03L7/18 ,  H04J3/0685 ,  H04J2203/0082 ,  H04J2203/0089 ,  H04L7/033

Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

Abstract translation: 本文给出了具有多个分频器路径的锁相环。 锁相环可用于提供宽范围的频率。 锁相环也可以用作时钟倍增器单元或时钟数据和恢复单元的一部分。

公开(公告)号：US08611379B2

公开(公告)日：2013-12-17

申请号：US13094484

申请日：2011-04-26

Applicant: Bharath Raghavan ,  Jun Cao ,  Afshin Momtaz

Inventor： Bharath Raghavan ,  Jun Cao ,  Afshin Momtaz

IPC: H04J3/04

CPC classification number: H03K5/07 ,  H03K2005/00071 ,  H03K2005/00208 ,  H03M9/00 ,  H04L7/0079 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033

Abstract: A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

Abstract translation: 可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器 用于在第一和第二频率处放大时钟信号。 谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。 第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。 延迟元件可以是电容器。 校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

公开(公告)号：US08483267B2

公开(公告)日：2013-07-09

申请号：US13152551

申请日：2011-06-03

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H04L27/10

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

Abstract: An equalizer that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. When the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.

Abstract translation: 一种均衡器，其补偿由通信系统中的发射机，接收机和/或通信信道产生的非线性效应。 非线性判决反馈均衡器通过基于先前接收到的符号在均衡系数之间进行选择来补偿对接收到的符号施加的非线性效应。 所接收的符号可以以基于二进制数系统的逻辑信号的形式表示。 当前一个接收到的符号是二进制零时，非线性判决反馈均衡器选择对应于二进制零的均衡系数来补偿被加载到接收符号上的非线性效应。 当先前接收到的符号是二进制符号时，非线性判决反馈均衡器选择对应于二进制符号的均衡系数来补偿被加载到接收符号上的非线性效应。