公开(公告)号：US06787906B1

公开(公告)日：2004-09-07

申请号：US09699589

申请日：2000-10-30

申请人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Sang-Ho Song ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

公开(公告)号：US06768148B1

公开(公告)日：2004-07-27

申请号：US10403480

申请日：2003-03-31

申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

IPC分类号： H01L2976

CPC分类号： H01L21/76237 ,  H01L21/823481

摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

公开(公告)号：US06727542B2

公开(公告)日：2004-04-27

申请号：US10246392

申请日：2002-09-19

申请人： Ki-Nam Kim ,  Byung-Jun Park

发明人： Ki-Nam Kim ,  Byung-Jun Park

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/55 ,  H01L28/91

摘要： A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate, a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area, a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistor, a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area is interposed, a guard-ring pattern, which are interposed between the cell area and the peripheral circuit area, surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern. The guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby step caused by manufacture of the stack-shaped capacitor are removed during a manufacturing process, and the contact fill for plate electrode is formed in the guard-ring pattern, and thereby the ground resistance of the capacitor is reduced, and the electrical characteristics of the memory device are improved.

摘要翻译： 提供半导体存储器件及其制造方法。 半导体存储器件包括用于隔离各个器件的氧化物层，其限定器件区域，使得在半导体衬底上的单元区域和外围电路区域彼此分离，由源极区域构成的多个MOS晶体管，漏极 形成在单元区域和外围电路区域中的区域和栅极，形成在多个MOS晶体管上并与MOS晶体管电连接的位线，堆叠形状的电容器，其由 第一电极，电介质层和第二电极，MOS晶体管和单元区域中的位线之间插入有保护环图形，其间插入在单元区域和外围电路区域之间，围绕单元区域 并且与外围电路区域分离，并且用于平板电极的接触填充物，其形成为保护环图案并与形成的第二电极接触 在内侧壁和保护环图案的底部。 保护环图案形成在单元区域和外围电路区域之间的边界周围，同时围绕单元区域，并且由此在制造过程中除去堆叠形电容器的制造所引起的步骤，并且板的接触填充 电极形成为保护环图案，从而降低了电容器的接地电阻，并提高了存储器件的电气特性。

公开(公告)号：US06613621B2

公开(公告)日：2003-09-02

申请号：US09803244

申请日：2001-03-09

申请人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

发明人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

IPC分类号： H01L21338

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/41783 ,  H01L29/66537 ,  H01L29/66545

摘要： Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

摘要翻译： 集成电路中的自对准触点可以形成在具有有源区的集成电路基板上。 可以在绝缘层中形成沟槽，并且可以在沟槽中形成导电材料到凹陷在凹槽中的水平。 绝缘材料可以形成在导电材料上的相对于绝缘层具有蚀刻选择性的凹槽中。 然后可以形成与活性区域自对准的接触。

公开(公告)号：US06515323B1

公开(公告)日：2003-02-04

申请号：US09698262

申请日：2000-10-30

申请人： Dong-Jin Jung ,  Ki-Nam Kim

发明人： Dong-Jin Jung ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A ferroelectric capacitor with a ferroelectric film having a relatively larger amount of titanium constituent than zirconate constituent improves ferroelectric characteristics. The method for fabricating the ferroelectric capacitor includes the step of performing a heat treatment in an oxygen atmosphere after forming a contact opening in an insulating layer which covers an already formed ferroelectric capacitor. This heat treatment in an oxygen atmosphere can minimize undesirable side effects resulting from a platinum electrode oxidizing the ferroelectric film components.

摘要翻译： 具有比锆酸盐成分更大量的钛组分的铁电体的铁电体电容器改善了铁电特性。 制造铁电电容器的方法包括在覆盖已经形成的铁电电容器的绝缘层中形成接触开口之后在氧气氛中进行热处理的步骤。 在氧气氛中的这种热处理可以使由铂电极氧化铁电体膜组分导致的不期望的副作用最小化。

公开(公告)号：US06420744B1

公开(公告)日：2002-07-16

申请号：US09712159

申请日：2000-11-15

申请人： Hyun-Ho Kim ,  Ki-Nam Kim

发明人： Hyun-Ho Kim ,  Ki-Nam Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  Y10S257/906

摘要： A method of forming a semiconductor device wherein a dummy cell region is defined at a periphery of a cell array region that includes a ferroelectric capacitor. A dummy capacitor is formed simultaneously at the dummy cell region when a ferroelectric capacitor is formed at the cell array region. Accordingly, plasma etching damage and electrical charge generation are concentrated on the dummy capacitor, thereby reducing plasma etching damage and electrical charge generation at the ferroelectric capacitor of the cell array region.

摘要翻译： 一种形成半导体器件的方法，其中在包括铁电电容器的单元阵列区域的外围限定虚拟单元区域。 当在单元阵列区域形成铁电电容器时，在虚设单元区域同时形成虚拟电容器。 因此，等离子体蚀刻损伤和电荷产生集中在虚拟电容器上，从而减少电池阵列区域的铁电电容器处的等离子体蚀刻损伤和电荷产生。

公开(公告)号：US06350649B1

公开(公告)日：2002-02-26

申请号：US09699849

申请日：2000-10-30

申请人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

发明人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10855

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer to be coupled to the underlying stud. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

摘要翻译： 在多层电路的层之间选择性地设置蚀刻停止层，以便在随后的制造过程中允许杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在要连接到下面的螺柱的上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

公开(公告)号：US6133116A

公开(公告)日：2000-10-17

申请号：US328708

申请日：1999-06-09

申请人： Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

发明人： Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8238

CPC分类号： H01L27/10844 ,  H01L21/762 ,  H01L21/765 ,  H01L27/10805 ,  H01L27/10873

摘要： Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.

摘要翻译： 通过在浅沟槽隔离（STI）中采用导电屏蔽，具有低掺杂衬底和有源宽度无关阈值电压的亚微米隔离间距DRAM的窄通道无效无效DRAM单元晶体管结构。 所得到的单元晶体管结构对通过STI的栅极和相邻存储节点结的寄生E场渗透是高度免疫的，并且将非常适合于Gbit规模DRAM技术。 导电屏蔽被负电压偏压，以便最小化衬底中的侧壁耗尽。

公开(公告)号：US08334556B2

公开(公告)日：2012-12-18

申请号：US12556648

申请日：2009-09-10

申请人： Joo-Young Lee ,  Ki-Nam Kim

发明人： Joo-Young Lee ,  Ki-Nam Kim

IPC分类号： H01L29/78 ,  H01L29/94

CPC分类号： H01L27/10876 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/10855 ,  H01L29/4236 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having an active region and an isolation region. A gate structure is provided on the semiconductor device. First and second impurity regions are provided in the substrate on both sides of the gate structure. A pad electrode is provided to contact the first impurity region. Because the pad electrode is provided on the first impurity region of the semiconductor device, the contact plug does not directly contact the active region. Accordingly, failures caused by damage to the active region may be prevented.

摘要翻译： 半导体器件包括具有有源区和隔离区的半导体衬底。 在半导体器件上设置栅极结构。 第一和第二杂质区设置在栅极结构两侧的衬底中。 提供焊盘电极以接触第一杂质区域。 由于焊盘电极设置在半导体器件的第一杂质区上，所以接触插塞不直接接触有源区。 因此，可以防止由有源区域的损坏引起的故障。

公开(公告)号：US20110300683A1

公开(公告)日：2011-12-08

申请号：US13137420

申请日：2011-08-15

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L45/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.