公开(公告)号：US20190148492A1

公开(公告)日：2019-05-16

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02576 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US10229999B2

公开(公告)日：2019-03-12

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US20190051735A1

公开(公告)日：2019-02-14

申请号：US15869349

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xusheng Wu ,  Jianwei Peng ,  Sipeng Gu ,  Hsien-Ching Lo

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

公开(公告)号：US20180366562A1

公开(公告)日：2018-12-20

申请号：US15627715

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Chengwen Pei ,  Ziyan Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: The disclosure is directed to methods of forming an integrated circuit structure and a related structure. One method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.

公开(公告)号：US10062772B2

公开(公告)日：2018-08-28

申请号：US15219370

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Xintuo Dai

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

公开(公告)号：US10050125B1

公开(公告)日：2018-08-14

申请号：US15676300

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Xusheng Wu ,  Hsien-Ching Lo

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.

公开(公告)号：US09991361B2

公开(公告)日：2018-06-05

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US20180122795A1

公开(公告)日：2018-05-03

申请号：US15338512

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ziyan Xu ,  Chengwen Pei ,  Xusheng Wu

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823418 ,  H01L27/10829 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7835

Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

公开(公告)号：US09935104B1

公开(公告)日：2018-04-03

申请号：US15589292

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US09761480B1

公开(公告)日：2017-09-12

申请号：US15047137

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Hui Zang

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847

Abstract: One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.