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41.发明申请公开(公告)号：US20150357441A1
公开(公告)日：2015-12-10
申请号：US14300506
申请日：2014-06-10
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Kejia Wang , Chun-Chen Yeh
CPC分类号： H01L29/66795 , H01L21/28114 , H01L21/32137 , H01L21/32139 , H01L29/66545 , H01L29/6656 , H01L29/7848 , H01L29/785
摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.
摘要翻译： 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。
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42.发明申请BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权用于集成电路晶体管器件的引出源漏极触点及其制造方法公开(公告)号：US20150357425A1
公开(公告)日：2015-12-10
申请号：US14297822
申请日：2014-06-06
发明人： Qing Liu , Ruilong Xie , Chun-Chen Yeh , Xiuyu Cai , William J. Taylor
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/823418 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.
摘要翻译： 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。
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公开(公告)号：US11374111B2
公开(公告)日：2022-06-28
申请号：US16743293
申请日：2020-01-15
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L21/768 , H01L29/08 , H01L29/161 , H01L29/165
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
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公开(公告)号：US10749031B2
公开(公告)日：2020-08-18
申请号：US15273778
申请日：2016-09-23
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/45 , H01L21/02 , H01L21/8234 , H01L21/768 , H01L21/285
摘要： A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
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公开(公告)号：US09922883B2
公开(公告)日：2018-03-20
申请号：US15180158
申请日：2016-06-13
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/08 , H01L29/786 , H01L21/84 , H01L21/768 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/7842 , H01L29/7848 , H01L29/786 , H01L29/78684
摘要： A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
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公开(公告)号：US09917162B2
公开(公告)日：2018-03-13
申请号：US15353352
申请日：2016-11-16
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L29/417 , H01L21/28 , H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L29/41741 , H01L21/02266 , H01L21/28114 , H01L21/28123 , H01L21/3065 , H01L21/308 , H01L29/42392 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
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公开(公告)号：US09711618B1
公开(公告)日：2017-07-18
申请号：US15087074
申请日：2016-03-31
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/02 , H01L29/66 , H01L29/78 , H01L29/423
CPC分类号： H01L29/41741 , H01L21/02266 , H01L21/28114 , H01L21/28123 , H01L21/3065 , H01L21/308 , H01L29/42392 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66666 , H01L29/66787 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78696
摘要： A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
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公开(公告)号：US20170084500A1
公开(公告)日：2017-03-23
申请号：US15366223
申请日：2016-12-01
IPC分类号： H01L21/8238 , H01L27/092 , H01L23/522 , H01L29/66
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
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公开(公告)号：US09564372B2
公开(公告)日：2017-02-07
申请号：US14740987
申请日：2015-06-16
IPC分类号： H01L21/82 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
摘要翻译： 制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。 第一电介质层被共形沉积，部分被去除以暴露S / D区域。 用于P型器件的暴露的S / D区域被硅化以形成衬垫。 第二电介质层被共形沉积。 在第二电介质层上形成电介质填充物。 接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。 通过打开保护层来暴露N型器件的S / D区域。 暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。 触点形成。
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50.发明申请公开(公告)号：US20170033023A1
公开(公告)日：2017-02-02
申请号：US15292184
申请日：2016-10-13
发明人： Tenko Yamashita , Chun-Chen Yeh , Hui Zang
CPC分类号： H01L22/32 , H01L21/76895 , H01L22/12 , H01L22/14 , H01L22/20 , H01L22/34 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L29/0649 , H01L29/66545 , H01L29/7851
摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
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