公开(公告)号：US09666582B1

公开(公告)日：2017-05-30

申请号：US15230632

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wai-Kin Li ,  Chengwen Pei

IPC: H01L21/8232 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L23/00

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/573 ,  H01L23/576 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/785

Abstract: Devices and methods are provided for constructing a semiconductor structure that implements a PUF (physical unclonable function) based on a FinFET structure. The PUF is based on a random pattern of merged and non-merged source and drain structures, which are formed on adjacent semiconductor fin structures of adjacent pairs of FinFET devices, as a result of process-induced variations in the epitaxial growth of source and drain structures on the semiconductor fin structures. The random pattern of merged and non-merged source and drain structures provides a random pattern of electrical open and short connections between pairs of semiconductor fin structures, wherein the random pattern of electrical open and short connections defines the physical unclonable function.

公开(公告)号：US09576914B2

公开(公告)日：2017-02-21

申请号：US14707442

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L27/088 ,  H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/02

CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US20160329287A1

公开(公告)日：2016-11-10

申请号：US14707442

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L23/00 ,  H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US09461042B2

公开(公告)日：2016-10-04

申请号：US14746017

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

公开(公告)号：US20160116435A1

公开(公告)日：2016-04-28

申请号：US14987329

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: G01N27/414 ,  H01L29/08

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US09240482B2

公开(公告)日：2016-01-19

申请号：US14476897

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/108

CPC classification number: H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平坦化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

公开(公告)号：US20150348974A1

公开(公告)日：2015-12-03

申请号：US14820667

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

IPC: H01L27/108 ,  H01L29/06

CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。

公开(公告)号：US08987078B2

公开(公告)日：2015-03-24

申请号：US14028957

申请日：2013-09-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。