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    Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
    45.
    发明授权
    Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits 有权
    栅极电介质结构的厚度缩小方法，形成集成电路的方法以及集成电路

    公开(公告)号：US09349823B2

    公开(公告)日：2016-05-24

    申请号：US14080533

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Kisik Choi

    IPC: H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L29/512 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517

    Abstract: Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

    Abstract translation: 提供了覆盖半导体衬底的栅介质结构的厚度缩小方法，形成集成电路的方法和集成电路。 覆盖半导体衬底的栅介质结构的厚度缩小方法包括提供半导体衬底。 在半导体衬底中或其上形成界面氧化物层。 在界面氧化物层上形成高k电介质层。 在高k电介质层的至少一部分上形成氧储存器。 在氧储存器上形成密封剂层。 包括设置在其上的氧气储存器的半导体基板被退火以通过高k电介质层和来自氧气存储器的界面氧化物层扩散氧。 退火在半导体衬底的位于氧储存器底部的部分处将界面氧化物层延伸到半导体衬底中，以在半导体衬底中或其上形成再生长界面区域。

    GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS
    48.
    发明申请
    GATE STRUCTURES FOR CMOS BASED INTEGRATED CIRCUIT PRODUCTS 审中-公开
    基于CMOS的集成电路产品的门控结构

    公开(公告)号：US20150348970A1

    公开(公告)日：2015-12-03

    申请号：US14822533

    申请日：2015-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Kisik Choi

    IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49

    CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/42356 ,  H01L29/4975

    Abstract: An integrated circuit product includes an NMOS transistor having a gate structure comprised of an NMOS gate insulation layer comprised of a high-k gate insulation material, an NMOS metal silicide region positioned above the NMOS gate insulation layer, and an NMOS metal layer positioned on the NMOS metal silicide region, and a PMOS transistor having a gate structure comprised of a PMOS gate insulation layer comprised of the high-k gate insulation material, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide region positioned above the first PMOS metal layer, wherein the PMOS metal silicide region and the NMOS metal silicide region are comprised of the same metal silicide, and a second PMOS metal layer positioned on the PMOS metal silicide region, wherein the NMOS metal layer and second PMOS metal layer are comprised of the same material.

    Abstract translation: 集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括由高k栅极绝缘材料构成的NMOS栅极绝缘层，位于NMOS栅极绝缘层上方的NMOS金属硅化物区域和位于NMOS栅极绝缘层上的NMOS金属层 NMOS金属硅化物区域和具有栅极结构的PMOS晶体管，PMOS栅绝缘层由高k栅极绝缘材料构成，第一PMOS金属层位于PMOS栅极绝缘层上，PMOS金属硅化物区域位于 第一PMOS金属层，其中PMOS金属硅化物区域和NMOS金属硅化物区域由相同的金属硅化物构成，以及位于PMOS金属硅化物区域上的第二PMOS金属层，其中NMOS金属层和第二PMOS金属层 由相同的材料组成。

    METHODS OF FORMING GATE STRUCTURES WITH MULTIPLE WORK FUNCTIONS AND THE RESULTING PRODUCTS
    50.
    发明申请
    METHODS OF FORMING GATE STRUCTURES WITH MULTIPLE WORK FUNCTIONS AND THE RESULTING PRODUCTS 有权
    用多种工作功能和结果产品形成门结构的方法

    公开(公告)号：US20150126023A1

    公开(公告)日：2015-05-07

    申请号：US14069782

    申请日：2013-11-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kisik Choi ,  Hoon Kim

    IPC: H01L21/28 ,  H01L29/51

    CPC classification number: H01L21/28158 ,  H01L21/28185 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

    Abstract translation: 本文公开的一种说明性方法包括去除用于NMOS和PMOS晶体管的牺牲栅极结构，从而限定NMOS和PMOS栅极空腔，在NMOS和PMOS栅极腔中形成高k栅绝缘层，在高层上形成镧系元素基材料层 -k栅极绝缘层，执行加热处理以将材料从镧系元素基材料层驱动到高k栅极绝缘层中，从而形成含镧系元素的高k栅极绝缘层 在每个NMOS和PMOS栅极腔中，以及在NMOS和PMOS栅极腔中的含镧系元素的高k栅极绝缘层之上形成栅电极结构。

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