公开(公告)号：US11322387B1

公开(公告)日：2022-05-03

申请号：US17069098

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Brett T. Cucci

IPC: H01L27/00 ,  H01L21/76 ,  H01L21/26 ,  H01L27/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US11315825B2

公开(公告)日：2022-04-26

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US11056382B2

公开(公告)日：2021-07-06

申请号：US15924444

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L29/78 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.

公开(公告)号：US11029465B1

公开(公告)日：2021-06-08

申请号：US16832023

申请日：2020-03-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michal Rakowski ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/28 ,  G02B6/293 ,  G02B6/02

Abstract: One illustrative device disclosed herein includes a micro-ring modulator that comprises an inner ring, an outer ring and a doped waveguide ring positioned between the inner ring and the outer ring. The device also includes an upper bus waveguide that is positioned vertically above at least a portion of the doped waveguide ring and at least a portion of the outer ring.

公开(公告)号：US20240178290A1

公开(公告)日：2024-05-30

申请号：US18059186

申请日：2022-11-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Megan Lydon-Nuhfer ,  Steven M. Shank ,  Aaron L. Vallett ,  Michel Abou-Khalil ,  Sarah A. McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/6653

Abstract: An integrated circuit (IC) structure includes a V-shaped cavity in a semiconductor substrate. A source region and a drain region are on opposing sides of the V-shaped cavity. A gate structure includes a gate dielectric layer, spacers, and a gate electrode on the gate dielectric layer between the spacers. The gate structure is fully within the V-shaped cavity. The IC structure provides a switch that finds advantageous application as part of a low noise amplifier. The IC structure provides a smaller gate width, decreased capacitance, increased gain and increased radio frequency (RF) performance compared to planar devices or devices without the gate structure fully within V-shaped cavity.

公开(公告)号：US20240085624A1

公开(公告)日：2024-03-14

申请号：US17944252

申请日：2022-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Judson Holt ,  Michal Rakowski ,  Bartlomiej Jan Pawlak

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13

Abstract: Structures including an electro-absorption modulator and methods of forming such structures. The structure comprises a waveguide core including a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section and the second tapered section are aligned along the longitudinal axis. The structure further comprises a first waveguide taper overlapping the first tapered section of the waveguide core, a second waveguide taper overlapping the second tapered section of the waveguide core, and a multiple-layer structure on the waveguide core between the first waveguide taper and the second waveguide taper.

公开(公告)号：US20230266544A1

公开(公告)日：2023-08-24

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US20230244030A1

公开(公告)日：2023-08-03

申请号：US17588470

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Takako Hirokawa

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/29338

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.

公开(公告)号：US20230188131A1

公开(公告)日：2023-06-15

申请号：US17643567

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H03K17/10 ,  H01L21/8234 ,  H01L27/12 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L21/823462 ,  H01L27/1203 ,  H03K17/693 ,  H03K2217/0018

Abstract: A structure includes a field effect transistor (FET) stack including a plurality of transistors over a buried insulator layer. A polysilicon isolation region is in a substrate below the FET stack and the buried insulator layer. A resistor network is in the polysilicon isolation region, the resistor network having a different resistivity than the polysilicon isolation region. The resistor network may include a resistive wire having a first width and a resistive pad within the resistive wire under each FET in the FET stack. Each resistive pad has a second width larger than the first width of the resistive wire. A length of the resistive wire is different aside each resistive pad to adjust a threshold voltage of an adjacent FET in the FET stack to a predetermined value to compensate for non-linear voltage distribution between an input and an output of the FET stack.

公开(公告)号：US20230154786A1

公开(公告)日：2023-05-18

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.