公开(公告)号：US09496250B2

公开(公告)日：2016-11-15

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  H01L29/73 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以包围器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。

公开(公告)号：US20160163685A1

公开(公告)日：2016-06-09

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以围绕器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。

公开(公告)号：US20160111352A1

公开(公告)日：2016-04-21

申请号：US14967965

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Abstract translation: 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US11380615B2

公开(公告)日：2022-07-05

申请号：US17118876

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Daisy A. Vaughn ,  Stephen R. Bosley ,  Zhong-Xiang He

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01G4/08 ,  H01G4/232 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

公开(公告)号：US20210066118A1

公开(公告)日：2021-03-04

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/265 ,  H01L29/06

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US20200176589A1

公开(公告)日：2020-06-04

申请号：US16207915

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Mark Goldstein

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/762 ,  C23C16/40 ,  C23C16/48

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.

公开(公告)号：US10446644B2

公开(公告)日：2019-10-15

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/732

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

公开(公告)号：US20190295881A1

公开(公告)日：2019-09-26

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US20190273028A1

公开(公告)日：2019-09-05

申请号：US15910603

申请日：2018-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

Abstract: Structures and methods associated with a silicon-on-insulator substrate are needed. A silicon-on-insulator substrate is provided that includes a device layer of single-crystal semiconductor material, a buried oxide layer, a handle wafer of single-crystal semiconductor material, and a non-single-crystal semiconductor layer between the handle wafer and the buried oxide layer. A trench is formed that extends through the device layer, the buried oxide layer, and the non-single-crystal semiconductor layer to the handle wafer. A semiconductor layer is epitaxially grown from the handle wafer to at least partially fill the trench, and a device structure is formed using at least a portion of the semiconductor layer.

公开(公告)号：US20190139841A1

公开(公告)日：2019-05-09

申请号：US15804165

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Patrick S. Spinney ,  Jeffrey C. Stamm

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L21/78

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.