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公开(公告)号：US20090111226A1
公开(公告)日：2009-04-30
申请号：US11926348
申请日：2007-10-29
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11534 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area.
摘要翻译： 提供了一种用于将非易失性存储器（NVM）电路与逻辑电路集成的方法。 该方法包括在NVM区域和衬底的逻辑区域上沉积第一层栅极材料层。 该方法还包括沉积包括彼此叠置的氮化物，氧化物和氮化物（ARC层）的多个邻接的牺牲层。 多个相邻的牺牲层用于在NVM区域中对存储晶体管的选择栅极和控制栅极进行图案化，并且多个相邻牺牲层的ARC层用于在逻辑区域中对逻辑晶体管的栅极进行图案化。
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公开(公告)号：US07091130B1
公开(公告)日：2006-08-15
申请号：US10876820
申请日：2004-06-25
IPC分类号： H01I21/302
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。
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43.发明授权Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor 有权具有具有不同密度的纳米晶体的不同非易失性存储器的半导体器件及其方法公开(公告)号：US08679912B2
公开(公告)日：2014-03-25
申请号：US13362697
申请日：2012-01-31
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。
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公开(公告)号：US08178406B2
公开(公告)日：2012-05-15
申请号：US11926323
申请日：2007-10-29
IPC分类号： H01L27/088 , H01L27/108
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L29/1037 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66636 , H01L29/66659
摘要： A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the first sidewall of the select gate. The thin layer of charge storage material is formed in which a first portion of the thin layer of charge storage material is formed in the first recess and a second portion of the thin layer of charge storage material is formed along the first sidewall of the first select gate. The control gate is formed over the first portion of the thin layer of charge storage material. The result is a semiconductor device useful a memory cell.
摘要翻译： 在半导体层上制造半导体器件的方法包括形成选择栅极，凹槽，电荷存储层和控制栅极。 选择栅极形成在半导体层上方具有第一侧壁。 凹槽形成在与选择栅极的第一侧壁相邻的半导体层中。 形成电荷存储材料的薄层，其中电荷存储材料薄层的第一部分形成在第一凹槽中，并且电荷存储材料薄层的第二部分沿着第一选择的第一侧壁形成 门。 控制栅极形成在电荷存储材料薄层的第一部分上。 结果是用于存储单元的半导体器件。
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公开(公告)号：US08035156B2
公开(公告)日：2011-10-11
申请号：US12241786
申请日：2008-09-30
IPC分类号： H01L29/792 , H01L21/8246 , H01L21/336
CPC分类号： H01L29/66833 , H01L29/42328 , H01L29/42344 , H01L29/66537 , H01L29/66636 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.
摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 选择栅极结构形成在衬底上。 控制栅结构具有侧壁。 在与侧壁相邻的区域中的衬底上形成外延层。 在外延层上形成电荷存储层。 在电荷存储层上形成控制栅极。 这允许在选择栅极下的原位掺杂外延层而不需要反掺杂。 避免反掺杂是有益的，因为反掺杂降低了电荷迁移率并增加了控制阈值电压的难度。 此外，可以在衬底中形成凹部，并且在凹部中形成外延层，并且可以在形成外延层之前通过凹槽进入在选择栅极下方的区域中的衬底中的晕圈注入。
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公开(公告)号：US20100128537A1
公开(公告)日：2010-05-27
申请号：US12277404
申请日：2008-11-25
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/10 , G11C16/349
摘要： A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.
摘要翻译： 包括非易失性存储单元的存储器系统。 存储器系统包括基于存储器系统的单元已经被擦除的次数将单元编程为第一阈值电压或第二阈值电压的程序电路。 在一个实施例中，当存储器系统的任何一组单元已被擦除特定次数时，阈值电压被降低。
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47.发明授权Non-volatile memory device with improved data retention and method therefor 有权具有改进的数据保留的非易失性存储器件及其方法公开(公告)号：US07432547B2
公开(公告)日：2008-10-07
申请号：US10779004
申请日：2004-02-13
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/42324 , H01L29/511 , H01L29/518 , H01L29/792
摘要： A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
摘要翻译： 半导体器件（30）包括下层绝缘层（34），上覆绝缘层（42）和在绝缘层（34,42）之间的电荷存储层（36）。 电荷存储层（36）和上覆绝缘层（42）形成存储电荷存储层（36）中至少大部分电荷的界面。 这可以通过在一个实施例中通过形成具有不同材料的电荷存储层（36）来实现，例如硅和硅锗层或n型和p型材料层。 在另一个实施例中，电荷存储层（36）包括分级的掺杂剂。 通过在电荷存储层（36）和上覆绝缘层（42）之间的界面处存储至少大部分电荷，通过下面的绝缘层的电荷泄漏减小，允许更薄的下层绝缘层（34） 要使用的。
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48.发明授权Method for forming a memory structure using a modified surface topography and structure thereof 有权使用改性表面形貌及其结构形成记忆结构的方法公开(公告)号：US06991984B2
公开(公告)日：2006-01-31
申请号：US10765804
申请日：2004-01-27
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/4925 , H01L29/4958
摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.
摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮动栅极16上。 在一个实施例中，分立元件22预先形成为气相并且通过静电力附着到半导体器件10。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。
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49.发明授权Non-volatile memory having a bias on the source electrode for HCI programming 有权用于HCI编程的源极上具有偏置的非易失性存储器公开(公告)号：US06909638B2
公开(公告)日：2005-06-21
申请号：US10426282
申请日：2003-04-30
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/30 , H01L20060101
摘要： Each cell of a memory is programmed by first using a source bias that is typically effective for programming the cells. If a cell is not successfully programmed in the first attempt, that is typically because a number of cells on the same column as that of the cell that did not successfully program have a relatively low threshold voltage, a low enough threshold voltage that these memory cells are biased, even with grounded gates, to be conductive. The vast majority of the cells do not have this problem, but it is common for there to be a few memory cells that do have this low threshold voltage characteristic. To overcome this, a different source bias is applied during subsequent programming attempts. Thus, the vast majority of the cells are programmed at the faster programming condition, and only the few that need it are programmed using the slower approach.
摘要翻译： 通过首先使用通常对编程单元有效的源偏置来对存储器的每个单元进行编程。 如果在第一次尝试中单元不成功编程，那通常是因为与未成功编程的单元相同列的单元数量具有相对较低的阈值电压，足够低的阈值电压，这些存储单元 偏置，即使是接地门，也是导电的。 绝大多数的电池没有这个问题，但是通常有几个具有这种低阈值电压特性的存储器单元。 为了克服这一点，在随后的编程尝试期间应用不同的源偏置。 因此，绝大多数单元被编程在更快的编程条件下，并且仅使用较慢的方法对需要的单元进行编程。
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50.发明申请公开(公告)号：US20120241839A1
公开(公告)日：2012-09-27
申请号：US13448531
申请日：2012-04-17
IPC分类号： H01L27/088
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.
摘要翻译： 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。
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