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公开(公告)号：US5978257A
公开(公告)日：1999-11-02
申请号：US28426
申请日：1998-02-24
IPC分类号： G11C11/15 , G11C11/16 , G11C11/56 , H01L21/8246
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16 , G11C11/5607 , H01L27/224 , G11C2211/5615 , G11C2211/5616
摘要： A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.
摘要翻译： 一种多态多层磁存储单元，包括第一导体，与第一导体接触的第一磁性层，第一磁性层上的绝缘层，绝缘层上的第二磁性层，与第二磁性体接触的第二导体 层，以及与单元相邻或接触的字线，以便提供磁场以沿着第一磁性层的长度部分地切换磁矢量。 通过使一条电流通过字线并通过第一和第二导体的第二电流足以切换第一和第二磁性层中的矢量来存储信息。 通过使读取电流通过足以通过第一和第二导体切换一层（而不是另一层）和感测电流通过电池的读取电流，并测量电池两端的电阻来实现感测。
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公开(公告)号：US5939941A
公开(公告)日：1999-08-17
申请号：US937775
申请日：1997-09-25
CPC分类号： H03F3/193 , H01L27/0605 , H01L29/7783 , H01L29/882
摘要： A high efficiency power amplifier includes an integrated circuit with a heterojunction interband tunneling field effect transistor (HITFET) amplifier coupled to receive high frequency (into the GHz) RF signals. The HITFET amplifier is constructed to receive the RF signal with a given frequency at the input terminal and to produce a substantially square wave signal at the given frequency at an output terminal in response to the RF signal applied to the input terminal. The gate of a switching FET connected as a class E amplifier is coupled to the output of the HITFET for receiving the square wave signal and an impedance matching output circuit is coupled to the drain of the switching FET.
摘要翻译： 高效率功率放大器包括具有耦合以接收高频（GHz）RF信号的异质结带间隧道场效应晶体管（HITFET）放大器的集成电路。 HITFET放大器被构造为响应于施加到输入端子的RF信号，在输入端子处以给定的频率在输入端子处接收RF信号并且在输出端子处以给定频率产生基本上方波的信号。 作为E级放大器连接的开关FET的栅极耦合到HITFET的输出端，用于接收方波信号，阻抗匹配输出电路耦合到开关FET的漏极。
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公开(公告)号：US5482875A
公开(公告)日：1996-01-09
申请号：US229266
申请日：1994-04-18
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08 , H01L29/10 , H01L29/778 , H01L29/80 , H01L21/335
CPC分类号： H01L29/7783 , H01L29/0891 , H01L29/1029 , Y10S148/072
摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
摘要翻译： 低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。 在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。 信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。 通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于 栅极源极电压大约在所需工作点处的相对最大值。
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公开(公告)号：US5061970A
公开(公告)日：1991-10-29
申请号：US533214
申请日：1990-06-04
申请人： Herbert Goronkin
发明人： Herbert Goronkin
IPC分类号： H01L21/20 , H01L21/338 , H01L29/15 , H01L29/201 , H01L29/778 , H01L29/812 , H01L39/22
CPC分类号： H01L29/155
摘要： A superlattice structure comprising a host quantum well with a plurality of mini quantum wells formed therein is provided. The host quantum well has a confined energy state E.sub.2 which lies very near a lower band energy V.sub.1 of the host well, while each of the mini quantum wells has a single confined energy level E.sub.1 which lies below V.sub.1. Charge carriers are provided to the quantum well by doping material in the barrier layers to provide modulation doping of the quantum well. The mini quantum wells contain at least one monolayer of another material within their boundaries. The monolayer material is preferably electrically inactive and is a source of phonons which are generated for the purpose of charge carrier-phonon coupling in order to cause charge carrier pairing. In a preferred embodiment a transfer quantum well is formed between the barrier region of the host quantum well and the outermost mini quantum wells. The transfer quantum well has an energy state which couples to the E.sub.1 energy state of the mini quantum wells and serves to transfer charge to the mini quantum wells.
摘要翻译： 提供了一种超晶格结构，其包括其中形成有多个微量子阱的主量子阱。 主量子阱具有非常靠近主井的较低频带能量V1的约束能态E2，而每个微量子阱具有位于V1以下的单个限制能级E1。 通过在阻挡层中掺杂材料来向量子阱提供电荷载体以提供量子阱的调制掺杂。 微量子阱在其边界内至少含有一个单层的另一种材料。 单层材料优选是电不活跃的，并且是为了引起电荷载流子配对而产生的电荷载体 - 声子耦合目的的声子源。 在优选实施例中，在主量子阱的阻挡区域和最外面的微量子阱之间形成传输量子阱。 传输量子阱具有耦合到微量子阱的E1能量状态并且用于将电荷传递到微量子阱的能量状态。
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公开(公告)号：US5016064A
公开(公告)日：1991-05-14
申请号：US411780
申请日：1989-09-25
申请人： Herbert Goronkin
发明人： Herbert Goronkin
IPC分类号： B01J19/00 , C30B29/40 , C30B29/68 , H01B12/06 , H01B13/00 , H01L29/06 , H01L29/15 , H01L29/267 , H01L39/02 , H01L39/24
CPC分类号： H01L29/155 , H01L29/267
摘要： An enhanced conductivity superlattice made from semiconductor materials provides enhanced conductivity. It is believed that conductivity can be enhanced sufficiently to produce superconductivity well above typical superconductivity temperatures of the semiconductor materials. The enhanced conductivity quantum well is a superlattice structure having a monolayer phonon generator sandwiched between layers of a host material. Barrier layers surround the host material to confine the host material electrons. In another embodiment, the monolayer may be located within the barrier layers. The monolayer generates phonons having an optical energy which is lower than the optical energy of the host material. The generated phonons couple with low energy electrons or holes to propagate without dissipation of electron energy.
摘要翻译： 由半导体材料制成的增强的电导率超晶格提供增强的导电性。 据信可以充分增强导电性以产生远高于半导体材料的典型超导温度的超导性。 增强的电导量子阱是具有夹在主体材料层之间的单层声子发生器的超晶格结构。 阻挡层围绕主体材料以限制主体材料电子。 在另一个实施方案中，单层可以位于阻挡层内。 单层产生具有低于主体材料的光能的光能的声子。 所产生的声子与低能电子或空穴耦合以传播而不耗散电子能量。
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公开(公告)号：US06594478B1
公开(公告)日：2003-07-15
申请号：US09706443
申请日：2000-11-03
申请人： Vijay Nair , Nada El Zein , Herbert Goronkin
发明人： Vijay Nair , Nada El Zein , Herbert Goronkin
IPC分类号： H04B128
CPC分类号： H03D7/125
摘要： A self oscillating mixer circuit includes a dual gate FET, an NDR device coupled to a first gate of the FET, and a first bias input circuit adapted to couple a first bias voltage across the NDR device. The first bias voltage controls operation of the NDR device within an NDR region of the V-I characteristic curve of the NDR device so that oscillations occur in the NDR device and the FET. The first bias input circuit is adjustable to adjust the applied first bias voltage so as to control frequency and amplitude of the oscillations. An RF input terminal and a second bias input circuit are coupled to supply a second bias voltage at the other gate terminal, which biases the FET at maximum gain so that RF signals applied to the RF input terminal are mixed with the oscillations.
摘要翻译： 自振荡混频器电路包括双栅极FET，耦合到FET的第一栅极的NDR器件和适于耦合NDR器件上的第一偏置电压的第一偏置输入电路。 第一偏置电压控制NDR器件在NDR器件的V-I特性曲线的NDR区域内的操作，从而在NDR器件和FET中发生振荡。 第一偏置输入电路是可调节的，以调节所施加的第一偏置电压，以便控制振荡的频率和振幅。 RF输入端子和第二偏置输入电路被耦合以在另一个栅极端子处提供第二偏置电压，其以最大增益偏置FET，使得施加到RF输入端子的RF信号与振荡混合。
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47.发明授权公开(公告)号：US06525957B1
公开(公告)日：2003-02-25
申请号：US10029085
申请日：2001-12-21
IPC分类号： G11C1115
CPC分类号： G11C11/5607 , G11C11/15
摘要： A magneto-electronic component includes a first current line (120, 520, 620, 820) for generating a first magnetic field, a magnetic memory cell (140, 540, 640, 740, 840), and a second current line (170, 470) for generating a second magnetic field and substantially perpendicular to the first current line. The magnetic memory cell includes a multi-state memory layer having a structure adjacent to the first current line such that a magnetic flux emanating from the multi-state memory layer is substantially confined to wrap around the first current line. The second current line is located adjacent to a portion of the multi-state memory layer.
摘要翻译： 磁电子部件包括用于产生第一磁场的第一电流线（120,520,620,820），磁存储单元（140,540,640,740,840）和第二电流线（170， 470），用于产生基本上垂直于第一电流线的第二磁场。 磁存储单元包括具有与第一电流线相邻的结构的多状态存储器层，使得从多状态存储层发出的磁通量基本上被限制在围绕第一电流线缠绕。 第二电流线位于多状态存储器层的一部分附近。
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公开(公告)号：US5942952A
公开(公告)日：1999-08-24
申请号：US903081
申请日：1997-07-30
CPC分类号： H03B7/06 , H01L27/0605 , H01L29/882 , H03B2200/0062 , H03B2201/02 , H03B7/143
摘要： A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.
摘要翻译： VCO包括具有与晶体管的源极端子串联耦合的多个负差分电阻器件的晶体管，其中每个器件具有负的差分电阻工作区域。 偏置电路耦合到漏极和栅极端子以及操作电压，其工作电压将振荡器设置为在负差分电阻器件中的至少一个的负差分电阻区域中工作，使得在输出端子处产生选定频率的振荡。 连接晶体管，多个N器件，DC偏置电路和工作电压，使得振荡器负差分电阻工作区域分别大于每个器件负差分工作区域的N倍。
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公开(公告)号：US5804458A
公开(公告)日：1998-09-08
申请号：US766076
申请日：1996-12-16
申请人： Saied N. Tehrani , Mark Durlam , Herbert Goronkin
发明人： Saied N. Tehrani , Mark Durlam , Herbert Goronkin
IPC分类号： H01L27/115 , H01L21/70
CPC分类号： H01L27/115 , H01L27/222 , H01L43/12
摘要： A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.
摘要翻译： 公开了一种制造多个间隔开的亚微米存储器单元的方法，包括以下步骤：在衬底形成上沉积磁阻系统，沉积和图形化第一材料层以形成侧壁，以及沉积第二层可选择的可蚀刻的 材料在第一层材料上蚀刻第二层材料以在第一材料层的侧壁上限定间隔物，使用间隔物作为掩模蚀刻磁阻系统以限定多个间隔开的亚微米磁存储器单元 并且在多个间隔开的亚微米磁存储器单元上沉积电触点。
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公开(公告)号：US5756154A
公开(公告)日：1998-05-26
申请号：US583329
申请日：1996-01-05
申请人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
IPC分类号： H01L21/316 , H01L21/20 , B05D1/32 , B05D3/00 , C08J7/18
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a substrate, and in a preferred embodiment a silicon substrate. The surface is hydrogen terminated (or hydrogenated) and a metal mask is positioned on the surface so as to define a growth area and an unmasked portion on the surface. Ozone is generated at the surface, at least in the unmasked area, by exposing the surface to a light having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating.
摘要翻译： 公开了一种在制造半导体器件期间掩蔽表面的方法，其包括提供衬底，并且在优选实施例中为硅衬底。 表面是氢封端（或氢化），并且金属掩模位于表面上，以便在表面上限定生长区域和未掩模部分。 通过将表面暴露于波长约185nm的光（氧吸收峰），至少在未掩模的区域中，在表面产生臭氧，以便在表面的未掩模部分上生长氧化膜。 除去金属掩模，然后氧化膜用作进一步操作的掩模，并且可以通过加热容易地原位除去。
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