公开(公告)号：US5920500A

公开(公告)日：1999-07-06

申请号：US702781

申请日：1996-08-23

申请人： Saied N. Tehrani ,  Xiaodong T. Zhu ,  Eugene Chen ,  Herbert Goronkin

发明人： Saied N. Tehrani ,  Xiaodong T. Zhu ,  Eugene Chen ,  Herbert Goronkin

IPC分类号： G11C11/15 ,  G11C11/14 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

CPC分类号： G11C11/14 ,  H01L27/222

摘要： A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).

摘要翻译： 磁性随机存取存储器（10）在半导体衬底（11）上具有多个堆叠的存储单元，每个单元基本上具有一部分磁性材料（12），字线（13）和感测线（14）。 上感测线（22）经由导体线（23）与欧姆接触电耦合到下感测线（12）。 为了读取和存储存储单元中的状态，上下文字线（13,18）被激活，从而将总磁场施加到磁性材料（11）的一部分。 这种堆叠式存储器结构允许磁性随机存取存储器（10）将更多的存储器单元集成在半导体衬底（11）上。

公开(公告)号：US5978257A

公开(公告)日：1999-11-02

申请号：US28426

申请日：1998-02-24

申请人： Xiaodong T. Zhu ,  Herbert Goronkin ,  Saied N. Tehrani

发明人： Xiaodong T. Zhu ,  Herbert Goronkin ,  Saied N. Tehrani

IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/56 ,  H01L21/8246

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  H01L27/224 ,  G11C2211/5615 ,  G11C2211/5616

摘要： A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

摘要翻译： 一种多态多层磁存储单元，包括第一导体，与第一导体接触的第一磁性层，第一磁性层上的绝缘层，绝缘层上的第二磁性层，与第二磁性体接触的第二导体 层，以及与单元相邻或接触的字线，以便提供磁场以沿着第一磁性层的长度部分地切换磁矢量。 通过使一条电流通过字线并通过第一和第二导体的第二电流足以切换第一和第二磁性层中的矢量来存储信息。 通过使读取电流通过足以通过第一和第二导体切换一层（而不是另一层）和感测电流通过电池的读取电流，并测量电池两端的电阻来实现感测。

公开(公告)号：US5294809A

公开(公告)日：1994-03-15

申请号：US65338

申请日：1993-05-24

申请人： Herbert Goronkin ,  Saied N. Tehrani ,  Jun Shen ,  Xiaodong T. Zhu

发明人： Herbert Goronkin ,  Saied N. Tehrani ,  Jun Shen ,  Xiaodong T. Zhu

IPC分类号： H01L29/88

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L29/882

摘要： A resonant tunneling diode having a quantum well sandwiched between first and second tunnel barrier layers and the quantum well and tunnel barrier layers sandwiched between an injection layer and a collector layer. The improvement includes a relatively thin layer of semiconductor material sandwiched between either the first tunnel barrier layer and the injection layer or the first tunnel barrier layer and the quantum well. The thin semiconductor layer has a valence band with an energy level lower than the valence band of the first tunnel barrier layer so as to prevent minority carriers from travelling toward the injection layer.

摘要翻译： 一种谐振隧道二极管，其具有夹在第一和第二隧道势垒层之间的量子阱以及夹在注入层和集电极层之间的量子阱和隧道势垒层。 该改进包括夹在第一隧道势垒层和注入层之间的相对薄的半导体材料层或第一隧道势垒层和量子阱。 薄半导体层具有能级低于第一隧道势垒层的价带的价带，以防止少数载流子朝向注入层行进。

公开(公告)号：US5552330A

公开(公告)日：1996-09-03

申请号：US386171

申请日：1995-02-09

申请人： Saied N. Tehrani ,  Herbert Goronkin ,  Jun Shen ,  Xiaodong T. Zhu

发明人： Saied N. Tehrani ,  Herbert Goronkin ,  Jun Shen ,  Xiaodong T. Zhu

IPC分类号： H01L29/68 ,  H01L21/20 ,  H01L21/334 ,  H01L27/06 ,  H01L29/205 ,  H01L29/76 ,  H01L21/265 ,  H01L21/44

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L27/0605 ,  H01L29/66939 ,  H01L29/7606

摘要： A resonant tunneling FET including a heterostructure FET with a channel layer having a first current contact and a control contact operatively coupled thereto and a resonant tunneling device, including a quantum well layer sandwiched between barrier layers with a resonant tunneling layer affixed to an opposite side of one barrier layer, operably affixed to the heterostructure FET to form a second current contact. The resonant tunneling FET being constructed from a material system which allows the fabrication of additional devices on the same substrate.

摘要翻译： 一种谐振隧穿FET，其包括具有第一电流接触的通道层和可操作地耦合到其上的控制触点的异质结构FET，以及谐振隧穿装置，其包括夹在阻挡层之间的量子阱层，其中谐振隧穿层固定在 一个阻挡层，可操作地固定到异质结构FET以形成第二电流接触。 谐振隧道FET由材料系统构成，其允许在同一衬底上制造附加器件。

公开(公告)号：US5489785A

公开(公告)日：1996-02-06

申请号：US209789

申请日：1994-03-11

申请人： Saied N. Tehrani ,  Jun Shen ,  Herbert Goronkin ,  Xiaodong T. Zhu

发明人： Saied N. Tehrani ,  Jun Shen ,  Herbert Goronkin ,  Xiaodong T. Zhu

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/205 ,  H01L29/737 ,  H01L27/12

CPC分类号： H01L29/7376 ,  B82Y10/00

摘要： A band-to-band resonant tunneling transistor including GaSb and InAs resonant tunneling layers separated by a thin barrier layer and a second InAs layer separated from the GaSb layer by another thin barrier layer. A terminal on the InAs resonant tunneling layer and a terminal on the second InAs layer. Leakage current reduction layers are positioned on the second InAs layer with a bias terminal positioned thereon. The InAs resonant tunneling layer has a plurality of quantized states which are misaligned with the ground state of the GaSb layer in a quiescent state, each of the quantized states of the InAs resonant tunneling layer are movable into alignment with the ground state of the GaSb layer to provide current flow through the transistor with the application of a specific potential to the terminal on the second InAs layer.

摘要翻译： 包括GaSb和InAs谐振隧道层的带对带谐振隧穿晶体管，其由薄的阻挡层和由另一个薄的阻挡层与GaSb层分离的第二InAs层隔开。 InAs谐振隧穿层上的一个端子和第二个InAs层上的一个端子。 漏电流减少层位于第二InAs层上，偏置端子位于其上。 InAs谐振隧穿层具有与处于静止状态的GaSb层的基态不对准的多个量化状态，InAs谐振隧穿层的每个量子化状态可移动地与GaSb层的基态对准 以通过向第二InAs层上的端子施加特定电位来提供流过晶体管的电流。

公开(公告)号：US5734605A

公开(公告)日：1998-03-31

申请号：US711751

申请日：1996-09-10

申请人： Xiaodong T. Zhu ,  Herbert Goronkin ,  Saied N. Tehrani

发明人： Xiaodong T. Zhu ,  Herbert Goronkin ,  Saied N. Tehrani

IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/56 ,  H01L21/8246

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/5607 ,  H01L27/224 ,  G11C2211/5615 ,  G11C2211/5616

摘要： A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

摘要翻译： 一种多态多层磁存储单元，包括第一导体，与第一导体接触的第一磁性层，第一磁性层上的绝缘层，绝缘层上的第二磁性层，与第二磁性体接触的第二导体 层，以及与单元相邻或接触的字线，以便提供磁场以沿着第一磁性层的长度部分地切换磁矢量。 通过使一条电流通过字线并通过第一和第二导体的第二电流足以切换第一和第二磁性层中的矢量来存储信息。 通过使读取电流通过足以通过第一和第二导体切换一层（而不是另一层）和感测电流通过电池的读取电流，并测量电池两端的电阻来实现感测。

公开(公告)号：US5563087A

公开(公告)日：1996-10-08

申请号：US494465

申请日：1995-06-26

申请人： Jun Shen ,  Saied N. Tehrani ,  Herbert Goronkin ,  Xiaodong T. Zhu

发明人： Jun Shen ,  Saied N. Tehrani ,  Herbert Goronkin ,  Xiaodong T. Zhu

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L27/11 ,  Y10S438/979

摘要： An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs layers. A TD including an AlSb layer sandwiched between InAS layers. A second InAs layer for each of the RITDs being integrally formed with a first InAs layer of the TD and a read/write terminal connected to a second InAs layer of the TD.

摘要翻译： 一种包括第一和第二RITD的SRAM，每个RITD均形成有异质结构，该异质结构包括夹在AlSb阻挡层之间的GaSb活性层，它们夹在InAs层之间，每个RITD具有连接到第一InAs层的触点。 包括夹在InAS层之间的AlSb层的TD。 用于与TD的第一InAs层整体形成的每个RITD的第二InAs层和连接到TD的第二InAs层的读/写端子。

公开(公告)号：US5414274A

公开(公告)日：1995-05-09

申请号：US96387

申请日：1993-07-26

申请人： Herbert Goronkin ,  Saied N. Tehrani ,  Jun Shen ,  Xiaodong T. Zhu

发明人： Herbert Goronkin ,  Saied N. Tehrani ,  Jun Shen ,  Xiaodong T. Zhu

IPC分类号： H01L29/06 ,  H01L29/68 ,  H01L29/772 ,  H01L29/205 ,  H01L29/88

CPC分类号： H01L29/772

摘要： A quantum multifunction transistor including a plurality of conduction layers of semiconductor material with a tunnel barrier layer sandwiched therebetween. The conduction layers each being very thin to form discrete energy levels, and the material being chosen so that discrete energy levels therein are not aligned across the tunnel barrier layer in an equilibrium state. A gate coupled to a portion of one of the conduction layers for aligning, in response to a voltage applied thereto, discrete energy levels in the conduction layers across the tunnel barrier layer, whereby majority carrier current flows through the transistor. Application of a higher voltage to the gate results in minority carrier current flow through the transistor.

摘要翻译： 一种量子多功能晶体管，包括多个导电层的半导体材料，其间夹有隧道势垒层。 导电层各自非常薄以形成离散的能级，并且选择材料使得其中的离散能级在平衡状态下不跨越隧道势垒层对准。 耦合到导电层之一的一部分的栅极，用于响应于施加到其上的电压，对准穿过隧道势垒层的导电层中的离散能级，从而多数载流子流过晶体管。 向栅极施加较高的电压导致少数载流子流过晶体管。

公开(公告)号：US5943574A

公开(公告)日：1999-08-24

申请号：US27915

申请日：1998-02-23

申请人： Saied N. Tehrani ,  Kumar Shiralagi ,  Herbert Goronkin

发明人： Saied N. Tehrani ,  Kumar Shiralagi ,  Herbert Goronkin

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092 ,  H01L29/786

CPC分类号： H01L29/6675 ,  H01L21/76838 ,  H01L27/0688 ,  H01L27/0922 ,  H01L29/78642

摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

摘要翻译： 一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。 绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。 通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。 在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。

公开(公告)号：US5748519A

公开(公告)日：1998-05-05

申请号：US766637

申请日：1996-12-13

申请人： Saied N. Tehrani ,  Herbert Goronkin

发明人： Saied N. Tehrani ,  Herbert Goronkin

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L21/78

CPC分类号： G11C11/15

摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.

摘要翻译： 提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。 每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。 一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。 因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。