公开(公告)号：US20080149940A1

公开(公告)日：2008-06-26

申请号：US11952407

申请日：2007-12-07

申请人： Daisuke SHIBATA ,  Kazushi Nakazawa ,  Masahiro Hikita ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Tsuyoshi Tanaka

发明人： Daisuke SHIBATA ,  Kazushi Nakazawa ,  Masahiro Hikita ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Tsuyoshi Tanaka

IPC分类号： H01L29/205

CPC分类号： H01L29/7786 ,  H01L21/76831 ,  H01L24/05 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板的主表面上的氮化物半导体层，具有沟道区域，电子沿着与所述主表面平行的方向漂移的沟道区域; 以及在氮化物半导体层中的有源区上彼此隔开形成的多个第一电极和多个第二电极。 在氮化物半导体层上形成层间绝缘膜。 层间绝缘膜具有分别暴露第一电极并具有平坦化顶表面的开口。 第一电极焊盘形成在层间绝缘膜中的有源区上方的区域中，并且通过相应的开口与暴露的第一电极电连接。

公开(公告)号：US20070114589A1

公开(公告)日：2007-05-24

申请号：US11600101

申请日：2006-11-16

申请人： Tetsuzo Ueda ,  Tsuyoshi Tanaka

发明人： Tetsuzo Ueda ,  Tsuyoshi Tanaka

IPC分类号： H01L29/94

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7787 ,  H01L2221/6835 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a first interconnection formed on the semiconductor layer through the first through hole and connected to one of the source electrode, the drain electrode and the gate electrode which is exposed in the first through hole; and a second interconnection formed on the insulating film through the second through hole and connected to another of the source electrode, the drain electrode and the gate electrode which is exposed in the second through hole. The first interconnection and the second interconnection face each other and form a microstrip line.

摘要翻译： 半导体集成电路器件包括：半导体层，其主表面上形成有源电极，漏电极和栅电极，并具有第一通孔; 形成为与所述半导体层接触并具有第二通孔的绝缘膜; 通过所述第一通孔形成在所述半导体层上并与所述第一通孔露出的所述源电极，所述漏电极和所述栅电极之一连接的第一互连; 以及通过第二通孔形成在绝缘膜上的第二互连，并与第二通孔中露出的源电极，漏电极和栅电极中的另一个连接。 第一互连和第二互连彼此面对并形成微带线。

公开(公告)号：US08592866B2

公开(公告)日：2013-11-26

申请号：US11600102

申请日：2006-11-16

申请人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

摘要翻译： 晶体管包括形成在基板上的第一半导体层，形成在第一半导体层上并具有比第一半导体层的带隙大的带隙的第二半导体层，形成在第二半导体层上并包含p型 杂质，形成为与控制层的至少一部分接触的栅极电极以及分别形成在控制层两侧的源电极和漏电极。 在控制层和第二半导体层之间形成由蚀刻率低于控制层的材料制成的第三半导体层。

公开(公告)号：US08264002B2

公开(公告)日：2012-09-11

申请号：US12880704

申请日：2010-09-13

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US07663161B2

公开(公告)日：2010-02-16

申请号：US11939899

申请日：2007-11-14

申请人： Kazuhiro Kaibara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Kazuhiro Kaibara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/739 ,  H01L29/732 ,  H01L29/22 ,  H01L33/00 ,  H01L29/06

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/432

摘要： A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

摘要翻译： 晶体管包括：第一半导体层和具有第一区域和第二区域的第二半导体层，其顺序地形成在衬底上; 形成在除了第一和第二区域之外的第二半导体层的区域上的第一p型半导体层; 以及形成在第一p型半导体层上的第二p型半导体层。 第一p型半导体层与漏电极分离，其间具有由第一区域构成的底部的第一沟槽和源极电极之间插入具有由第二区域构成的底部的第二沟槽。

公开(公告)号：US20060273347A1

公开(公告)日：2006-12-07

申请号：US11433734

申请日：2006-05-15

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US07612426B2

公开(公告)日：2009-11-03

申请号：US11272878

申请日：2005-11-15

申请人： Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L21/26506 ,  H01L27/0605 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/66143

摘要： A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.

摘要翻译： 肖特基势垒二极管包括在半导体衬底上连续形成的第一半导体层和形成在第一和第二半导体层与半导体衬底之间的缓冲层的第二半导体层。 在第二半导体层上形成有彼此间隔开的肖特基电极和欧姆电极，在半导体基板的背面形成背面电极。 肖特基电极或欧姆电极通过贯穿至少缓冲层的通孔电连接到背面电极。

公开(公告)号：US07339207B2

公开(公告)日：2008-03-04

申请号：US11455631

申请日：2006-06-20

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。

公开(公告)号：US20070096151A1

公开(公告)日：2007-05-03

申请号：US11602267

申请日：2006-11-21

申请人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L31/00 ,  H01L29/739

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/42304 ,  H01L29/7371

摘要： A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

摘要翻译： 双极晶体管包括：具有本征基极区域和外部基极区域的第一半导体层; 以及第二半导体层，其具有位于本征基极区上的作为发射极区域或集电极区域的部分。 使用与第二半导体层相同的半导体材料在非本征基极区域上提供电容膜。 在第一半导体层上形成基极以覆盖电容膜和外部基极区。

公开(公告)号：US07187014B2

公开(公告)日：2007-03-06

申请号：US10862452

申请日：2004-06-08

申请人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

发明人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC分类号： H01L29/772

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

摘要翻译： 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。