公开(公告)号：US06465818B1

公开(公告)日：2002-10-15

申请号：US09478057

申请日：2000-01-05

申请人： Hideo Kato

发明人： Hideo Kato

IPC分类号： G11C502

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/24

摘要： A memory cell array 1 is divided into two banks BANK 1 and BANK 2 for performing a dual operation. The division into banks is accomplished by dividing main bit lines MBL of the memory cell array 1 into upper and lower parts. On both end portions of the memory cell array 1 in the directions of the bit lines, sense amplifier circuits 2a and 2b connected to the divided parts of main bit lines MBL, respectively, are arranged. By changing the wiring design of the main bit lines MBL, the capacities of the banks BANK 1 and BANK 2 are changed.

摘要翻译： 存储单元阵列1被分成两个银行BANK 1和BANK 2，用于执行双重操作。 通过将存储单元阵列1的主位线MBL分成上部和下部来实现划分为存储体。 在位线方向上的存储单元阵列1的两端部，分别连接到主位线MBL的分割部分的读出放大器电路2a和2b。 通过改变主位线MBL的布线设计，银行BANK 1和BANK 2的容量改变。

公开(公告)号：US06317274B1

公开(公告)日：2001-11-13

申请号：US09533691

申请日：2000-03-23

申请人： Hideo Kato ,  Hiroshi Maehara

发明人： Hideo Kato ,  Hiroshi Maehara

IPC分类号： G02B308

CPC分类号： G03F7/70058 ,  G02B5/1866 ,  G02B5/1876 ,  G03F7/70216

摘要： An optical element includes a first substrate having a diffractive surface or a surface structure with a surface level difference, a second substrate for covering the diffractive surface or the surface structure to provide a shield therefor, and a groove provided at the diffractive surface or the surface structure, and extending from a central portion to a peripheral portion thereof, for discharging or replacing a gas at the diffractive surface or the surface structure therethrough.

摘要翻译： 光学元件包括具有衍射面或具有表面水平差的表面结构的第一衬底，用于覆盖衍射表面或表面结构以提供其屏蔽的第二衬底，以及设置在衍射表面或表面处的凹槽 结构，并且从中心部分延伸到其周边部分，用于排出或替换通过其中的衍射表面或表面结构处的气体。

公开(公告)号：US6075035A

公开(公告)日：2000-06-13

申请号：US11752

申请日：1998-02-23

申请人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Noriyuki Kado ,  Nobuhiko Iwasaki ,  Hiroyuki Nishino ,  Makoto Takeshita

发明人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Noriyuki Kado ,  Nobuhiko Iwasaki ,  Hiroyuki Nishino ,  Makoto Takeshita

IPC分类号： C07D491/04 ,  C07D491/044 ,  A01N43/42

CPC分类号： C07D491/04

摘要： Dihydrate crystal of 3-[4-(8-fluoro-5,11-dihydrobenz[b]oxepino[4,3-b]pyridin-11-ylidene)piperidino]propionic acid providing high-intensity diffraction peaks at diffraction angles (2.theta.) of about 4.2.degree., 17.0.degree., and 21.3.degree. in a powder X-ray diffraction profile; a medicament comprising the dihydrate crystal; and a process for preparing the dihydrate crystal which comprises the steps of treating a crystalline substance containing an anhydride crystal of the above compound with hydrous acetone, and subjecting the product to drying treatment and moistening treatment.

摘要翻译： PCT No.PCT / JP96 / 02352 Sec。 371日期1998年2月23日 102（e）1998年2月23日PCT PCT 1996年8月23日PCT公布。 出版物WO97 / 09330 日期1997年3月13日提供高强度衍射峰的3- [4-（8-氟-5,11-二氢苯并[b]氧杂环庚烯并[4,3-b]吡啶-11-亚基）哌啶子基]丙酸的二水合晶体 在衍射角（2θ）为约4.2°，17.0°和21.3°的粉末X射线衍射图中; 包含二水合物晶体的药物; 以及制备二水合物晶体的方法，包括以下步骤：用含水丙酮处理含有上述化合物的无水物结晶的结晶物质，并对产物进行干燥处理和润湿处理。

公开(公告)号：US5793696A

公开(公告)日：1998-08-11

申请号：US826820

申请日：1997-04-08

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

公开(公告)号：US5615165A

公开(公告)日：1997-03-25

申请号：US576564

申请日：1995-12-21

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

公开(公告)号：US5534362A

公开(公告)日：1996-07-09

申请号：US419417

申请日：1995-04-10

申请人： Takafumi Okamoto ,  Manabu Tanaka ,  Ichiro Baba ,  Hideo Kato ,  Norimasa Kawagoe

发明人： Takafumi Okamoto ,  Manabu Tanaka ,  Ichiro Baba ,  Hideo Kato ,  Norimasa Kawagoe

IPC分类号： H01M8/02 ,  H01M8/04 ,  H01M8/24

CPC分类号： H01M8/242 ,  H01M8/04007 ,  H01M8/247 ,  H01M2300/0082 ,  H01M8/0202 ,  H01M8/0204 ,  H01M8/04014 ,  H01M8/04029 ,  H01M8/04119 ,  H01M8/04291 ,  Y10T29/4911

摘要： A fuel cell stack having unit cells and separators, in which each unit cell comprises a solid polymer electrolyte membrane having a pair of electrode catalysts attached on both surfaces, and a pair of collectors, each made of a rigid body, being in contact with respective electrode catalysts, and each of the separators comprises a pair of pressure generating plates defining therebetween a pressure chamber to which a pressurized fluid is introduced, the pressure generating plates being deformed by the pressurized fluid and pressed against the adjacent respective collectors.

公开(公告)号：US5506813A

公开(公告)日：1996-04-09

申请号：US235371

申请日：1994-04-29

申请人： Yoshio Mochizuki ,  Hideo Kato ,  Nobutake Sugiura

发明人： Yoshio Mochizuki ,  Hideo Kato ,  Nobutake Sugiura

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C17/12 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/112 ,  G11C7/00 ,  H01L27/10

CPC分类号： H01L27/1126 ,  G11C11/56 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112 ,  G11C16/0491 ,  G11C16/24 ,  G11C7/18

摘要： In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current. Thereby, an information amount per one element can be made equal to a plural-bit information amount, and the bit data capacity can be increased.

摘要翻译： 在具有电池阵列结构的半导体存储装置中，其中泄漏电流的发生减少并且感测时的余量增加，以矩阵形式排列并具有四个阈值中的任一个的多个存储晶体管构成列方向 。 银行构成存储单元阵列。 Al的主位线通过第一选择晶体管连接到三个子位线。 Al的主地线通过第二选择晶体管连接到两个子接地线。 银行选择行和字线形成为跨越主位线和主地线。 选择晶体管的栅极连接到选择线，并且一个选择线连接到一个选择晶体管。 每个子位线和子接地线具有构成一个存储体的一列存储晶体管。 在存储单元阵列之间形成氧化硅膜的分离区（未示出）等，以防止漏电流。 从而，可以使每一个元素的信息量等于多位信息量，并且可以增加位数据容量。

公开(公告)号：US5500422A

公开(公告)日：1996-03-19

申请号：US348808

申请日：1994-11-28

申请人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Nobuhiko Iwasaki ,  Hiroyuki Nishino ,  Makoto Takeshita

发明人： Yasuo Ito ,  Hideo Kato ,  Shingo Yasuda ,  Nobuhiko Iwasaki ,  Hiroyuki Nishino ,  Makoto Takeshita

IPC分类号： C07D211/58 ,  C07D451/04 ,  C07D451/14 ,  C07D211/36 ,  A61K31/445

CPC分类号： C07D451/04 ,  C07D211/58 ,  C07D451/14

摘要： A benzamide derivative represented by the following formula: ##STR1## wherein R.sup.1 represents a hydrogen atom or a lower alkanoyl group; R.sup.2 represents a hydrogen atom or a halogen atom; R.sup.3 represents a lower alkoxy group; R.sup.4 represents a hydrogen atom or a lower alkyl group; R.sup.5 represents a hydrogen atom, a lower alkyl group, or a lower alkoxy group; A represents C.sub.1 -C.sub.7 alkylene group which may optionally be substituted with a lower alkyl group; X represents a methylene group, an oxygen atom, or a sulfur atom; m represents an integer of from 0 to 3; n represents an integer of from 0 to 3; and p represents an integer of from 0 to 2 and a pharmacologically acceptable salt thereof is provided. These compounds are useful since they have gastrointestinal stimulating activity, and a pharmaceutical composition comprising said compound is useful for the treatment of gastrointestinal diseases.

摘要翻译： 由下式表示的苯甲酰胺衍生物：其中R 1表示氢原子或低级烷酰基; R2表示氢原子或卤素原子; R3表示低级烷氧基; R4代表氢原子或低级烷基; R5表示氢原子，低级烷基或低级烷氧基; A表示可以被低级烷基取代的C1-C7亚烷基; X表示亚甲基，氧原子或硫原子; m表示0〜3的整数， n表示0〜3的整数， p表示0〜2的整数，并且其药理学上可接受的盐。 这些化合物是有用的，因为它们具有胃肠道刺激活性，并且包含所述化合物的药物组合物可用于治疗胃肠道疾病。

公开(公告)号：US5499769A

公开(公告)日：1996-03-19

申请号：US196216

申请日：1994-03-15

申请人： Masanori Namiki ,  Kazuyoshi Mori ,  Hideo Kato

发明人： Masanori Namiki ,  Kazuyoshi Mori ,  Hideo Kato

IPC分类号： F02M51/08 ,  F02M51/06 ,  F02M61/18 ,  F02M69/00 ,  F02M69/04

CPC分类号： F02M61/1853 ,  F02M51/061 ,  F02M61/18 ,  F02M69/044 ,  F02M69/047

摘要： A fuel injection valve wherein fuel sprays discharged from a fuel injection hole are impacted with auxiliary air introduced from outside to thereby promote atomization and subsequent vaporization of the fuel sprays, is provided with fuel spray guide passages for each guiding one of the fuel sprays. As a result, the fuel sprays discharged from the fuel injection holes, are impacted by the auxiliary air to thereby promote atomization and subsequent vaporization thereof, and are guided by the inner walls of the fuel spray guide passages, to thereby control the diffusion and spray direction of the fuel sprays. The cross-sectional shape of the fuel sprays is thus controlled to an optimum shape so that adhesion of fuel to the inner wall of the intake port is minimized, thereby improving combustion, and in particular reducing hydrocarbon emissions and improving fuel consumption.

摘要翻译： PCT No.PCT / JP93 / 00996 Sec。 371日期1994年3月15日 102（e）1994年3月15日PCT提交1993年7月16日PCT公布。 出版物WO94 / 02736 日期：1994年2月3日。一种燃料喷射阀，其中从燃料喷射孔排出的燃料喷射被从外部引入的辅助空气冲击，从而促进雾化和随后的燃料喷雾蒸发，设置有用于每个引导的燃料喷射引导通道 其中一种燃油喷雾。 结果，从燃料喷射孔排出的燃油喷射被辅助空气冲击，从而促使其雾化并随后蒸发，并由燃料喷雾引导通道的内壁引导，从而控制扩散和喷雾 燃料喷雾方向。 因此，燃料喷雾的横截面形状被控制到最佳形状，使得燃料对进气口的内壁的附着力最小化，从而改善燃烧，特别是减少碳氢化合物排放并改善燃料消耗。

公开(公告)号：US5420822A

公开(公告)日：1995-05-30

申请号：US218629

申请日：1994-03-28

申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly.

摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。