公开(公告)号：US07790553B2

公开(公告)日：2010-09-07

申请号：US12170687

申请日：2008-07-10

申请人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

发明人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

摘要翻译： 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

公开(公告)号：US07466010B2

公开(公告)日：2008-12-16

申请号：US11175094

申请日：2005-07-05

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Marwan H. Khater ,  Richard P. Volant

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Marwan H. Khater ,  Richard P. Volant

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

摘要翻译： 本发明提供一种具有凸起的非本征基极硅化物和自对准的发射极接触边界的双极晶体管。 与不包括自对准硅化物和自对准发射极接触边界的双极晶体管相比，本发明的双极晶体管表现出减小的寄生效应。 本发明还涉及制造本发明的双极晶体管结构的方法。 在本发明的方法中，块状发射极多晶硅区域代替常规的T形发射极多晶硅。

公开(公告)号：US07425754B2

公开(公告)日：2008-09-16

申请号：US10708340

申请日：2004-02-25

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory G. Freeman ,  David R. Greenberg ,  Marwan H. Khater ,  William R. Tonti

IPC分类号： H01L27/102

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

公开(公告)号：US07355221B2

公开(公告)日：2008-04-08

申请号：US10908448

申请日：2005-05-12

申请人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

发明人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

公开(公告)号：US07348250B2

公开(公告)日：2008-03-25

申请号：US11041845

申请日：2005-01-22

申请人： Gregory G. Freeman

发明人： Gregory G. Freeman

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8228

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L29/1004 ,  H01L29/7378

摘要： Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has lower ramp rate.

摘要翻译： 采用SiGe技术的双极集成电路结合了提供掩模选择型双极晶体管。 高性能/高可变性类型具有薄的基极，其中来自发射极的扩散与基极集电极结附近的Ge浓度的“斜坡”内的基极掺杂剂扩散相交，并且较低的性能/较低变异性类型具有额外的外延 使得发射极扩散与Ge斜坡相交，其中斜坡具有较低的斜率。

公开(公告)号：US07102205B2

公开(公告)日：2006-09-05

申请号：US10931660

申请日：2004-09-01

申请人： Dureseti Chidambarrao ,  Gregory G. Freeman ,  Marwan H. Khater

发明人： Dureseti Chidambarrao ,  Gregory G. Freeman ,  Marwan H. Khater

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

摘要： A method of increasing mobility of charge carriers in a bipolar device comprises the steps of: creating compressive strain in the device to increase mobility of holes in an intrinsic base of the device; and creating tensile strain in the device to increase mobility of electrons in the intrinsic base of the device. The compressive and tensile strains are created by forming a stress layer in close proximity to the intrinsic base of the device. The stress layer is at least partially embedded in a base layer of the device, adjacent an emitter structure of the device. The stress layer has different lattice constant than the intrinsic base. Method and apparatus are described.

摘要翻译： 增加双极器件中电荷载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件的本征基极中的孔的迁移率; 并且在器件中产生拉伸应变以增加器件本征基底中电子的迁移率。 压缩和拉伸应变是通过在紧邻该装置的固有基底的位置形成应力层来产生的。 应力层至少部分地嵌入在器件的基底层中，与器件的发射极结构相邻。 应力层具有与内在基体不同的晶格常数。 描述了方法和装置。

公开(公告)号：US06979884B2

公开(公告)日：2005-12-27

申请号：US10727945

申请日：2003-12-04

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Marwan H. Khater ,  Richard P. Volant

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Marwan H. Khater ,  Richard P. Volant

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

公开(公告)号：US06492238B1

公开(公告)日：2002-12-10

申请号：US09887310

申请日：2001-06-22

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng-Yi Huang ,  Adam D. Ticknor

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng-Yi Huang ,  Adam D. Ticknor

IPC分类号： H01L2100

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623

摘要： A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

摘要翻译： 用于形成具有凸起的外部基极，发射极和与具有栅极的CMOS电路集成的集电极的双极晶体管的工艺。 提供具有CMOS和双极区域的中间半导体结构。 在双极区域内提供本征基层。 基底氧化物跨越形成，牺牲发射极堆叠硅层沉积在CMOS和双极区两者上。 施加光致抗蚀剂以保护双极区域，并且蚀刻该结构以从CMOS区域去除牺牲层，使得双极区域上的牺牲层的顶表面基本上与CMOS区域的顶表面齐平。 最后，沉积抛光停止层，其具有穿过适于随后的化学机械抛光（CMP）的CMOS和双极区域的基本平坦的顶表面，以形成凸起的外在基体。

公开(公告)号：US06472288B2

公开(公告)日：2002-10-29

申请号：US09733330

申请日：2000-12-08

申请人： Gregory G. Freeman ,  K. T. Schonenberg ,  Kenneth J. Stein ,  Seshadri Subbanna

发明人： Gregory G. Freeman ,  K. T. Schonenberg ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC分类号： H01L21331

CPC分类号： H01L27/0823 ,  H01L21/8222 ,  Y10S438/933

摘要： Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

摘要翻译： 不同设计的双极晶体管，特别是针对不同高频应用优化的设计，通过用于锗，硼和/或碳的不同材料浓度分布的用于外延生长的单独的基底层形成工艺在相同的衬底上形成。 通过使用可以选择性地蚀刻到硅上的蚀刻停止来避免通过包括相应的集电极区域的硅衬底的蚀刻来促进单个生长层通过低温工艺的外延生长。 退火处理可以在各基底层的生长之间进行和/或在所有晶体管基本上完成之后集体执行。